SMJ320C6203 Datasheet, PDF (43/81 Pages) Texas Instruments – FIXED POINT SIGNAL PROCESSOR

SMJ320C6203
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
ASYNCHRONOUS MEMORY TIMING (CONTINUED)
SGUS033 – FEBRUARY 2002
switching characteristics over recommended operating conditions for asynchronous memory
cycles^{†‡§¶} (see Figure 15 – Figure 18)
NO.
PARAMETER
MIN TYP
MAX UNIT
1 tosu(SELV-AREL) Output setup time, select signals valid to ARE low
RS x P – 2
ns
2 toh(AREH-SELIV) Output hold time, ARE high to select signals invalid
*RH x P – 2
ns
5 tw(AREL)
Pulse width, ARE low
RST x P
ns
8 td(ARDYH-AREH) Delay time, ARDY high to ARE high
12 tosu(SELV-AWEL) Output setup time, select signals valid to AWE low
13 toh(AWEH-SELIV) Output hold time, AWE high to select signals invalid
14 tw(AWEL)
Pulse width, AWE low
*3P
*4P + 5 ns
WS x P – 3
ns
*WH x P – 2
ns
WST x P
ns
17 td(ARDYH-AWEH) Delay time, ARDY high to AWE high
*3P
*4P + 5 ns
*This parameter is not production tested.
† _{RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are}
programmed via the EMIF CE space control registers.
‡ _{P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.}
§ _{The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use ARDY input to extend strobe width.}
¶ _{Select signals include: CEx, BE[3:0], EA[21:2], AOE; and for writes, include ED[31:0], with the exception that CEx can stay active for an additional}
7P ns following the end of the cycle.
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