SMJ320C6203 Datasheet, PDF (40/81 Pages) Texas Instruments – FIXED POINT SIGNAL PROCESSOR

SMJ320C6203
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS033 – FEBRUARY 2002
INPUT AND OUTPUT CLOCKS
timing requirements for CLKIN (PLL used)^{†‡§} (see Figure 11)
NO.
1 tc(CLKIN) Cycle time, CLKIN
2 tw(CLKINH) Pulse duration, CLKIN high
3 tw(CLKINL) Pulse duration, CLKIN low
4 tt(CLKIN) Transition time, CLKIN
*This parameter is not production tested.
† _{The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.}
‡ _{M = the PLL multiplier factor (x4, x6, x7, x8, x9, x10, or x11).}
§ _{C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.}
MIN
5xM
*0.45C
*0.45C
MAX
*0.5
UNIT
ns
ns
ns
ns
timing requirements for CLKIN [PLL bypassed (x1)]^†¶ (see Figure 11)
NO.
MIN
MAX UNIT
1 tc(CLKIN) Cycle time, CLKIN
5
ns
2 tw(CLKINH) Pulse duration, CLKIN high
*0.45C
ns
3 tw(CLKINL) Pulse duration, CLKIN low
*0.45C
ns
4 tt(CLKIN) Transition time, CLKIN
*0.6 ns
*This parameter is not production tested.
† _{The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.}
¶ _{C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns. The maximum CLKIN cycle time in PLL bypass mode}
(x1) is 200 MHz.
CLKIN
1
4
2
3
4
Figure 11. CLKIN Timings
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