SMJ320C6203 Datasheet, PDF (67/81 Pages) Texas Instruments – FIXED POINT SIGNAL PROCESSOR

SMJ320C6203
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS033 – FEBRUARY 2002
EXPANSION BUS ASYNCHRONOUS HOST-PORT TIMING
timing requirements with external device as asynchronous bus master^† (see Figure 42 and
Figure 43)
NO.
MIN MAX UNIT
1 tw(XCSL)
Pulse duration, XCS low
2 tw(XCSH)
3 tsu(XSEL-XCSL)
4 th(XCSL-XSEL)
Pulse duration, XCS high
Setup time, expansion bus select signals^‡ valid before XCS low
Hold time, expansion bus select signals^‡ valid after XCS low
10 th(XRYL-XCSL)
11 tsu(XBEV-XCSH)
12 th(XCSH-XBEV)
Hold time, XCS low after XRDY low
Setup time, XBE[3:0]/XA[5:2] valid before XCS high^§
Hold time, XBE[3:0]/XA[5:2] valid after XCS high^§
13 tsu(XDV-XCSH)
Setup time, XDx valid before XCS high
14 th(XCSH-XDV)
Hold time, XDx valid after XCS high
*This parameter is not production tested.
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.}
‡ _{Expansion bus select signals include XCNTL and XR/W.}
§ _{XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.}
4P
ns
4P
ns
1
ns
3.4
ns
*P + 1.5
ns
1
ns
3
ns
1
ns
3
ns
switching characteristics over recommended operating conditions with external device as
asynchronous bus master^† (see Figure 42 and Figure 43)
NO.
PARAMETER
5 td(XCSL-XDLZ)
Delay time, XCS low to XDx low impedance
6 td(XCSH-XDIV)
Delay time, XCS high to XDx invalid
7 td(XCSH-XDHZ)
Delay time, XCS high to XDx high impedance
8 td(XRYL-XDV)
Delay time, XRDY low to XDx valid
9 td(XCSH-XRYH)
Delay time, XCS high to XRDY high
*This parameter is not production tested.
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.}
MIN
*0
*0
*–4
*0
MAX
*12
*4P
*1
12
UNIT
ns
ns
ns
ns
ns
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