SMJ320C6203 Datasheet, PDF (72/81 Pages) Texas Instruments – FIXED POINT SIGNAL PROCESSOR

SMJ320C6203
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS033 – FEBRUARY 2002
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
CLKS
CLKR
FSR (int)
FSR (ext)
DR
CLKX
FSX (int)
FSX (ext)
FSX (XDATDLY=00b)
DX
1
2
3
3
4
4
5
6
7
2
3
3
Bit(n-1)
9
8
(n-2)
11
10
12
Bit 0
14
13
Bit(n-1)
13
(n-2)
Figure 46. McBSP Timings
timing requirements for FSR when GSYNC = 1 (see Figure 47)
NO.
1 tsu(FRH-CKSH) Setup time, FSR high before CLKS high
2 th(CKSH-FRH) Hold time, FSR high after CLKS high
*This parameter is not production tested.
(n-3)
(n-3)
MIN MAX UNIT
*4
ns
*4
ns
CLKS
FSR external
CLKR/X (no need to resync)
CLKR/X (needs resync)
1
2
Figure 47. FSR Timing When GSYNC = 1
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