SMJ320C6203 Datasheet, PDF (34/81 Pages) Texas Instruments – FIXED POINT SIGNAL PROCESSOR

SMJ320C6203
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS033 – FEBRUARY 2002
clock PLL
Most of the internal C6203 clocks are generated from a single source through the CLKIN pin. This source clock
either drives the PLL, which multiplies the source clock in frequency to generate the internal CPU clock, or
bypasses the PLL to become the internal CPU clock.
To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Figure 5,
and Table 16 through Table 17 show the external PLL circuitry for either x1 (PLL bypass) or x4 PLL multiply
modes. Figure 6 shows the external PLL circuitry for a system with ONLY x1 (PLL bypass) mode.
To minimize the clock jitter, a single clean power supply should power both the C6203 device and the external
clock oscillator circuit. Noise coupling into PLLF directly impacts PLL clock jitter. The minimum CLKIN rise and
fall times should also be observed. For the input clock timing requirements, see the input and output clocks
electricals section. Table 15 lists some examples of compatible CLKIN external clock sources:
Table 15. Compatible CLKIN External Clock Sources
COMPATIBLE PARTS FOR
EXTERNAL CLOCK SOURCES (CLKIN)
Oscillators
PLL
PART NUMBER
JITO-2
STA series, ST4100 series
SG-636
342
MK1711-S, ICS525-02
MANUFACTURER
Fox Electronix
SaRonix Corporation
Epson America
Corning Frequency Control
Integrated Circuit Systems
3.3V
EMI Filter
C3
10 mF
C4
0.1 mF
PLLV
CLKMODE0
CLKMODE1
CLKMODE2
CLKIN
PLLMULT
PLL
PLLCLK
CLKIN
LOOP FILTER
Internal to C6203
1
CPU
0
CLOCK
(For the PLL Options
and CLKMODE pins setup,
see Table 16 and Table 17)
C2
C1
R1
NOTES: A. Keep the lead length and the number of vias between pin PLLF, pin PLLG, R1, C1, and C2 to a minimum. In addition, place all PLL
components (R1, C1, C2, C3, C4, and EMI Filter) as close to the C6000 DSP device as possible. Best performance is achieved
with the PLL components on a single side of the board without jumpers, switches, or components other than the ones shown.
B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (R1, C1, C2, C3, C4,
and the EMI Filter).
C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.
Figure 5. External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode
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