K5L5628JTM Datasheet, PDF (97/98 Pages) Samsung semiconductor – 256M Bit (16M x16) Synchronous Burst , Multi Bank NOR Flash / 128M Bit(8M x16) Synchronous Burst UtRAM

K5L5628JT(B)M
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MCP MEMORY
TRANSITION TIMING WAVEFORM BETWEEN READ AND WRITE
Fig.39 SYNCH. BURST WRITE to SYNCH. BURST READ TIMING WAVEFORM
[Latency=5, Burst Length=4](MRS=VIH)
CLK
ADV
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
T
tADVS
tADVH
tBEADV
Address
CS
WE
tAS(B)
tAH(B)
Valid
Don’t Care
tCSS(B)
tBC
tWES
tWEH
tAS(B)
Valid
tAH(B)
tCSS(B)
tBC
OE
LB, UB
Data in
tBS
tBH
Latency 5
tDS
D0 D1 D2 D3
tDHC
Data out
tWL
tWH
WAIT
High-Z
High-Z
tWZ tWL
tOEL
tBEL
High-Z
Latency 5
tCD
tOH
tHZ
tWH
DQ0 DQ1 DQ2 DQ3
(SYNCHRONOUS BURST READ & WRITE CYCLE)
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
should be met.
2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
/WAIT High(tWH) : Data available(driven by Latency-1 clock)
/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)
3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
4. Burst Cycle Time(tBC) should not be over 2.5µs.
Table 43. BURST WRITE to BURST READ AC CHARACTERISTICS
Symbol
Speed
Units
Symbol
Min
Max
Min
tBEADV
7
-
ns
Speed
Max
Units
97
Revision 1.0
November 2004