K5L5628JTM Datasheet, PDF (43/98 Pages) Samsung semiconductor – 256M Bit (16M x16) Synchronous Burst , Multi Bank NOR Flash / 128M Bit(8M x16) Synchronous Burst UtRAM

K5L5628JT(B)M
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MCP MEMORY
DQ6 : Toggle Bit
Toggle bit is another option to detect whether an Internal Routine is in progress or completed. Once the device is at a busy state,
DQ6 will toggle. Toggling DQ6 will stop after the device completes its Internal Routine. If the device is in the Erase/Program Suspend
Mode, an attempt to read an address that belongs to a block that is being erased or programmed will produce a high output of DQ6.
If an address belongs to a block that is not being erased or programmed, toggling is halted and valid data is produced at DQ6. If an
attempt is made to program a protected block, DQ6 toggles for approximately 1us and the device then returns to the Read Mode
without changing the data in the block. If an attempt is made to erase a protected block, DQ6 toggles for approximately 100µs and
the device then returns to the Read Mode without erasing the data in the block.
DQ5 : Exceed Timing Limits
If the Internal Program/Erase Routine extends beyond the timing limits, DQ5 will go High, indicating program/erase failure.
DQ3 : Block Erase Timer
The status of the multi-block erase operation can be detected via the DQ3 pin. DQ3 will go High if 50µs of the block erase time win-
dow expires. In this case, the Internal Erase Routine will initiate the erase operation.Therefore, the device will not accept further write
commands until the erase operation is completed. DQ3 is Low if the block erase time window is not expired. Within the block erase
time window, an additional block erase command (30H) can be accepted. To confirm that the block erase command has been
accepted, the software may check the status of DQ3 following each block erase command.
DQ2 : Toggle Bit 2
The device generates a toggling pulse in DQ2 only if an Internal Erase Routine or an Erase/Program Suspend is in progress. When
the device executes the Internal Erase Routine, DQ2 toggles only if an erasing block is read. Although the Internal Erase Routine is
in the Exceeded Time Limits, DQ2 toggles only if an erasing block in the Exceeded Time Limits is read. When the device is in the
Erase/Program Suspend mode, DQ2 toggles only if an address in the erasing or programming block is read. If a non-erasing or non-
programmed block address is read during the Erase/Program Suspend mode, then DQ2 will produce valid data. DQ2 will go High if
the user tries to program a non-erase suspend block while the device is in the Erase Suspend mode.
RDY: Ready
Normally the RDY signal is used to indicate if new burst data is available at the rising edge of the clock cycle or not. If RDY is low
state, data is not valid at expected time, and if high state, data is valid. Note that, if CE is low and OE is high, the RDY is high state.
Start
Start
Yes
DQ7 = Data ?
No
No
DQ5 = 1 ?
Yes
Yes
DQ7 = Data ?
No
Fail
Pass
Figure 1. Data Polling Algorithms
No
DQ6 = Toggle ?
Yes
No
DQ5 = 1 ?
Yes
No
DQ6 = Toggle ?
Yes
Fail
Pass
Figure 2. Toggle Bit Algorithms
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Revision 1.0
November 2004