K5L5628JTM Datasheet, PDF (63/98 Pages) Samsung semiconductor – 256M Bit (16M x16) Synchronous Burst , Multi Bank NOR Flash / 128M Bit(8M x16) Synchronous Burst UtRAM

K5L5628JT(B)M
PPrreelliimmiinnaarryy
MCP MEMORY
Case2 : Start from "4N+1" address group
A0-A23
Data Bus
5 cycle for initial access shown.(54MHz case)
D
E
F
10
11
12
13
CLK
D
AVD
CE
OE
RDY
E
F
10
11
12
13
14
Additional 1 Cycle for First Word Boundary
tOER
tCEZ
tOEZ
Case 3 : Start from "4N+2" address group
5 cycle for initial access shown.(54MHz case)
A0-A23
Data Bus
E
F
10
11
12
13
CLK
E
AVD
F
10
11
12
13
14
Additional 2 Cycle for First Word Boundary
CE
tCEZ
OE
tOER
tOEZ
RDY
Notes:
1. Address boundry occurs every 16 words beginning at address 00000FH , 00001FH , 00002FH , etc.
2. Address 000000H is also a boundry crossing.
3. No additional clock cycles are needed except for 1st boundary crossing.
Figure 16. Crossing of first word boundary in burst read mode.
63
Revision 1.0
November 2004