K5L5628JTM Datasheet, PDF (34/98 Pages) Samsung semiconductor – 256M Bit (16M x16) Synchronous Burst , Multi Bank NOR Flash / 128M Bit(8M x16) Synchronous Burst UtRAM

K5L5628JT(B)M
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MCP MEMORY
COMMAND DEFINITIONS
The device operates by selecting and executing its operational modes. Each operational mode has its own command set. In order to
select a certain mode, a proper command with specific address and data sequences must be written into the command register. Writ-
ing incorrect information which include address and data or writing an improper command will reset the device to the read mode. The
defined valid register command sequences are stated in Table 5.
Table 5. Command Sequences
Command Definitions
Asynchronous Read
Reset(Note 5)
Autoselect
Manufacturer ID(Note 6)
Autoselect
Device ID(Note 6)
Autoselect
Block Protection Verify(Note 7)
Autoselect
Handshaking(Note 6, 8)
Program
Unlock Bypass
Unlock Bypass Program(Note 9)
Unlock Bypass Block Erase(Note 9)
Unlock Bypass Chip Erase(Note 9)
Unlock Bypass Reset
Quadruple word Accelerated Program(Note 10)
Chip Erase
Block Erase
Erase Suspend (Note 11)
Erase Resume (Note 12)
Program Suspend (Note13)
Program Resume (Note12)
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
Cycle
1
1
4
4
4
4
4
3
2
2
2
2
5
6
6
1
1
1
1
1st Cycle 2nd Cycle 3rd Cycle
RA
RD
XXXH
F0H
555H
2AAH (DA)555H
AAH
55H
90H
555H
2AAH (DA)555H
AAH
55H
90H
555H
2AAH (BA)555H
AAH
55H
90H
555H
2AAH (DA)555H
AAH
55H
90H
555H
2AAH
555H
AAH
55H
A0H
555H
2AAH
555H
AAH
55H
20H
XXX
PA
A0H
PD
XXX
BA
80H
30H
XXXH
XXXH
80H
10H
XXXH
XXXH
90H
00H
XXX
PA1
PA2
A5H
PD1
PD2
555H
2AAH
555H
AAH
55H
80H
555H
2AAH
555H
AAH
55H
80H
(DA)XXXH
B0H
(DA)XXXH
30H
(DA)XXXH
B0H
(DA)XXXH
30H
4th Cycle
(DA)X00H
ECH
(DA)X01H
Note6
(BA)X02H
00H / 01H
(DA)X03H
0H/1H
PA
PD
PA3
PD3
555H
AAH
555H
AAH
5th Cycle 6th Cycle
PA4
PD4
2AAH
55H
2AAH
55H
555H
10H
BA
30H
34
Revision 1.0
November 2004