K5L5628JTM Datasheet, PDF (33/98 Pages) Samsung semiconductor – 256M Bit (16M x16) Synchronous Burst , Multi Bank NOR Flash / 128M Bit(8M x16) Synchronous Burst UtRAM

K5L5628JT(B)M
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MCP MEMORY
PRODUCT INTRODUCTION
The device is a 256Mbit (268,435,456 bits) NOR-type Burst Flash memory. The device features 1.8V single voltage power supply
operating within the range of 1.7V to 1.95V. The device is programmed by using the Channel Hot Electron (CHE) injection mecha-
nism which is used to program EPROMs. The device is erased electrically by using Fowler-Nordheim tunneling mechanism. To pro-
vide highly flexible erase and program capability, the device adopts a block memory architecture that divides its memory array into
519 blocks (32-Kword x 511 , 4-Kword x 8, ). Programming is done in units of 16 bits (Word). All bits of data in one or multiple blocks
can be erased when the device executes the erase operation. To prevent the device from accidental erasing or over-writing the pro-
grammed data, 519 memory blocks can be hardware protected. Regarding read access time, at 54MHz, the device provides a burst
access of 14.5ns with initial access times of 88.5ns at 30pF. At 66MHz, the device provides a burst access of 11ns with initial access
times of 70ns at 30pF. The command set of device is compatible with standard Flash devices. The device uses Chip Enable (CE),
Write Enable (WE), Address Valid(AVD) and Output Enable (OE) to control asynchronous read and write operation. For burst opera-
tions, the device additionally requires Ready (RDY) and Clock (CLK). Device operations are executed by selective command codes.
The command codes to be combined with addresses and data are sequentially written to the command registers using microproces-
sor write timing. The command codes serve as inputs to an internal state machine which controls the program/erase circuitry. Regis-
ter contents also internally latch addresses and data necessary to execute the program and erase operations. The device is
implemented with Internal Program/Erase Routines to execute the program/erase operations. The Internal Program/Erase Routines
are invoked by program/erase command sequences. The Internal Program Routine automatically programs and verifies data at
specified addresses. The Internal Erase Routine automatically pre-programs the memory cell which is not programmed and then
executes the erase operation. The device has means to indicate the status of completion of program/erase operations. The status
can be indicated via Data polling of DQ7, or the Toggle bit (DQ6). Once the operations have been completed, the device automati-
cally resets itself to the read mode. The device requires only 30mA as burst and asynchronous mode read current and 15 mA for pro-
gram/erase operations.
Table 4. Device Bus Operations
Operation
Asynchronous Read Operation
CE OE WE A0-22 DQ0-15 RESET CLK AVD
L
L
H
Add In
I/O
H
L
L
Write
L
H
Add In
I/O
H
L
X
Standby
H
X
X
X
High-Z
H
X
X
Hardware Reset
X
X
X
X
High-Z
L
X
X
Load Initial Burst Address
L
H
H
Add In
X
H
Burst Read Operation
Terminate Burst Read Cycle
L
L
H
X
Burst
DOUT
H
H
H
X
X
X
High-Z
H
X
X
Terminate Burst Read Cycle via RESET
X
X
X
X
High-Z
L
X
X
Terminate Current Burst Read Cycle and Start
New Burst Read Cycle
L
H
H
Add In
I/O
H
Note : L=VIL (Low), H=VIH (High), X=Don’t Care.
33
Revision 1.0
November 2004