K5L5628JTM Datasheet, PDF (48/98 Pages) Samsung semiconductor – 256M Bit (16M x16) Synchronous Burst , Multi Bank NOR Flash / 128M Bit(8M x16) Synchronous Burst UtRAM

K5L5628JT(B)M
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MCP MEMORY
SWITCHING WAVEFORMS
5 cycles for initial access shown.
CR setting : A14=0, A13=0, A12=1
tCES
15.2 ns typ.
tCEZ
CE
CLK
AVD
A0-A23
DQ0-DQ15
OE
Hi-Z
RDY
tAVDS
tAVDH
tACS
tACH
tOER
tIAA
tRDYA
tBDH
tBA
Da Da+1 Da+2 Da+3
tRDYS
Hi-Z
Da+n
tOEZ
Hi-Z
Figure 3. Burst Mode Read (66 MHz)
Note: In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high.
5 cycles for initial access shown.
CR setting : A14=0, A13=0, A12=1
tCES
18.5 ns typ.
tCEZ
CE
CLK
AVD
A0-A23
DQ0-DQ15
tAVDS
tAVDH
tACS
tACH
OE
Hi-Z
RDY
tOER
tIAA
tRDYA
tBDH
tBA
Da Da+1 Da+2 Da+3
tRDYS
Hi-Z
Da+n
tOEZ
Hi-Z
Figure 4. Burst Mode Read (54 MHz)
Note: In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high.
48
Revision 1.0
November 2004