K5L5628JTM Datasheet, PDF (41/98 Pages) Samsung semiconductor – 256M Bit (16M x16) Synchronous Burst , Multi Bank NOR Flash / 128M Bit(8M x16) Synchronous Burst UtRAM

K5L5628JT(B)M
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MCP MEMORY
Erase Suspend / Resume
The Erase Suspend command interrupts the Block Erase to read or program data in a block that is not being erased. Also, it is pos-
sible to protect or unprotect of the block that is not being erased in erase suspend mode. The Erase Suspend command is only valid
during the Block Erase operation including the time window of 50 us. The Erase Suspend command is not valid while the Chip Erase
or the Internal Program Routine sequence is running. When the Erase Suspend command is written during a Block Erase operation,
the device requires a maximum of 20 us(recovery time) to suspend the erase operation. Therefore system must wait for 20us(recov-
ery time) to read the data from the bank which include the block being erased. Otherwise, system can read the data immediately from
a bank which don’t include the block being erased without recovery time(max. 20us) after Erase Suspend command. And, after the
maximum 20us recovery time, the device is availble for programming data in a block that is not being erased. But, when the Erase
Suspend command is written during the block erase time window (50 us) , the device immediately terminates the block erase time
window and suspends the erase operation. The system may also write the autoselect command sequence when the device is in the
Erase Suspend mode. When the Erase Resume command is executed, the Block Erase operation will resume. When the Erase Sus-
pend or Erase Resume command is executed, the addresses are in Don't Care state.
Program Suspend / Resume
The device provides the Program Suspend/Resume mode. This mode is used to enable Data Read by suspending the Program
operation. The device accepts a Program Suspend command in Program mode(including Program operations performed during
Erase Suspend) but other commands are ignored. After input of the Program Suspend command, 2us is needed to enter the Pro-
gram Suspend Read mode. Therefore system must wait for 2us(recovery time) to read the data from the bank which include the
block being programmed. Othwewise, system can read the data immediately from a bank which don't include block being pro-
grammed without ecovery time(max. 2us) after Program Suspend command. Like an Erase Suspend mode, the device can be
returned to Program mode by using a Program Resume command.
Read While Write Operation
The device is capable of reading data from one bank while writing in the other banks. This is so called the Read While Write opera-
tion. An erase operation may also be suspended to read from or program to another location within the same bank(except the block
being erased). The Read While Write operation is prohibited during the chip erase operation. Figure 12 shows how read and write
cycles may be initiated for simultaneous operation with zero latency. Refer to the DC Characteristics table for read-while-write current
specifications.
OTP Block Region
The OTP Block feature provides a 256-byte Flash memory region that enables permanent part identification through an Electronic
Serial Number (ESN). The OTP Block is customer lockable and shipped with itself unlocked, allowing customers to untilize the that
block in any manner they choose. The customer-lockable OTP Block has the Protection Verify Bit (DQ0) set to a "0" for Unlocked
state or a "1" for Locked state.
The system accesses the OTP Block through a command sequence (see "Enter OTP Block / Exit OTP Block Command sequence"
at Table8). After the system has written the "Enter OTP Block" Command sequence, it may read the OTP Block by using the
addresses (FFFF80h~FFFFFFh) normally and may check the Protection Verify Bit (DQ0) by using the "Autoselect Block Protection
Verify" Command sequence with OTP Block address. This mode of operation continues until the system issues the "Exit OTP Block"
Command suquence, a hardware reset or until power is removed from the device. On power-up, or following a hardware reset, the
device reverts to sending commands to main blocks. Note that the Accelerated function and unlock bypass modes are not available
when the OTP Block is enabled.
Customer Lockable
In a Customer lockable device, The OTP Block is one-time programmable and can be locked only once. Note that the Accelerated
programming and Unlock bypass functions are not available when programming the OTP Block. Locking operation to the OTP Block
is started by writing the "Enter OTP Block" Command sequence, and then the "Block Protection" Command sqeunce (Table 8) with
an OTP Block address. Hardware reset terminates Locking operation, and then makes exiting from OTP Block. The Locking opera-
tion has to be above 100us.
The OTP Block Lock operation must be used with caution since, once locked, there is no procedure available for unlocking
and none of the bits in the OTP Block space can be modified in any way.
Low VCC Write Inhibit
To avoid initiation of a write cycle during Vcc power-up and power-down, a write cycle is locked out for Vcc less than VLKO. If the Vcc
< VLKO (Lock-Out Voltage), the command register and all internal program/erase circuits are disabled. Under this condition the
device will reset itself to the read mode.Subsequent writes will be ignored until the Vcc level is greater than VLKO. It is the user’s
responsibility to ensure that the control pins are logically correct to prevent unintentional writes when Vcc is above VLKO.
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Revision 1.0
November 2004