K5L5628JTM Datasheet, PDF (38/98 Pages) Samsung semiconductor – 256M Bit (16M x16) Synchronous Burst , Multi Bank NOR Flash / 128M Bit(8M x16) Synchronous Burst UtRAM

K5L5628JT(B)M
PPrreelliimmiinnaarryy
MCP MEMORY
The Programmable wait state setting instructs the device to set a particular number of clock cycles for the initial access in burst
mode. Note that hardware reset will set the wait state to the default setting, that is 7 initial cycles.
Burst Read Mode Setting
The device supports five different burst read modes : continuous linear mode, 8 and 16 word linear burst modes with wrap and 8 and
16 word linear burst modes with no-wrap.
RDY Configuration
By default, the RDY pin will be high whenever there is valid data on the output. The device can be set so that RDY goes active one
data cycle before active data. Address bit A18 determine this setting. Note that RDY always go high with valid data in case of word
boundary crossing.
Table 8. Burst Address Sequences
Start
Addr.
Continuous Burst
Burst Address Sequence(Decimal)
8-word Burst
16-word Burst
0
0-1-2-3-4-5-6...
0-1-2-3-4-5-6-7
0-1-2-3-4-....-13-14-15
1
Wrap
2
1-2-3-4-5-6-7...
2-3-4-5-6-7-8...
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
1-2-3-4-5-....-14-15-0
2-3-4-5-6-....-15-0-1
.
.
.
.
.
.
.
.
0
0-1-2-3-4-5-6...
0-1-2-3-4-5-6-7
0-1-2-3-4-....-13-14-15
1
No-wrap
2
1-2-3-4-5-6-7...
2-3-4-5-6-7-8...
1-2-3-4-5-6-7-8
2-3-4-5-6-7-8-9
1-2-3-4-5-....-14-15-16
2-3-4-5-6-....-15-16-17
.
.
.
.
.
.
.
.
Autoselect Mode
By writing the autoselect command sequences to the system, the device enters the autoselect mode. This mode can be read only by
asynchronous read mode. The system can then read autoselect codes from the internal register(which is separate from the memory
array). Standard asynchronous read cycle timings apply in this mode. The device offers the Autoselect mode to identify manufacturer
and device type by reading a binary code. In addition, this mode allows the host system to verify the block protection or unprotection.
Table 5 shows the address and data requirements. The autoselect command sequence may be written to an address within a bank
that is in the read mode, erase-suspend-read mode or program-suspend-read mode. The autoselect command may not be written
while the device is actively programming or erasing in the device. The autoselect command sequence is initiated by first writing two
unlock cycles. This is followed by a third write cycle that contains the address and the autoselect command. Note that the block
address is needed for the verification of block protection. The system may read at any address within the same bank any number of
times without initiating another autoselect command sequence. And the burst read should be prohibited during Autoselect Mode. To
terminate the autoselect operation, write Reset command(F0H) into the command register.
Table 9. Autoselct Mode Description
Description
Address
Read Data
Manufacturer ID
(DA) + 00H
ECH
Device ID
(DA) + 01H
22FCH(Top Boot Block), 22FDH(Bottom Boot Block)
Block Protection/Unprotection (BA) + 02H
01H (protected), 00H (unprotected)
Handshaking
(DA) + 03H
0H : handshaking, 1H : non-handshaking
Standby Mode
When the CE and RESET inputs are both held at VCC ± 0.2V or the system is not reading or writing, the device enters Stand-by mode
to minimize the power consumption. In this mode, the device outputs are placed in the high impedence state, independent of the OE
input. When the device is in either of these standby modes, the device requires standard access time (tCE ) for read access before it
is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is
completed. ICC5 in the DC Characteristics table represents the standby current specification.
Automatic Sleep Mode
The device features Automatic Sleep Mode to minimize the device power consumption during both asynchronous and burst mode.
When addresses remain stable for tAA+60ns, the device automatically enables this mode. The automatic sleep mode is independent
of the CE, WE, and OE control signals. In a sleep mode, output data is latched and always available to the system. When addresses
are changed, the device provides new data without wait time. Automatic sleep mode current is equal to standby mode current.
38
Revision 1.0
November 2004