K5L5628JTM Datasheet, PDF (81/98 Pages) Samsung semiconductor – 256M Bit (16M x16) Synchronous Burst , Multi Bank NOR Flash / 128M Bit(8M x16) Synchronous Burst UtRAM

K5L5628JT(B)M
PPrreelliimmiinnaarryy
MCP MEMORY
ASYNCHRONOUS WRITE TIMING WAVEFORM
Fig.18 TIMING WAVEFORM OF WRITE CYCLE(2)(MRS=VIH, OE=VIH, WAIT=High-Z, UB & LB Controlled)
Address
CS
UB, LB
WE
Data in
tWC
tWR
tCW
tAW
tBW
tAS
tWP
tDW
tDH
Data Valid
Data out
High-Z
High-Z
(ASYNCHRONOUS WRITE CYCLE - UB & LB Controlled)
1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB
or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition
when CS goes high or WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high.
5. In asynchronous write cycle, Clock, ADV and WAIT signals are ignored.
Table 22. ASYNCHRONOUS WRITE AC CHARACTERISTICS(UB & LB Controlled)
Symbol
Speed
Min
Max
tWC
70
-
tCW
60
-
tAW
60
-
tBW
60
-
tWP
55¹⁾
-
1. tWP(min)=70ns for continuous write operation over 50 times.
Units
ns
ns
ns
ns
ns
Symbol
tAS
tWR
tDW
tDH
Speed
Min
0
0
30
0
Max
-
-
-
-
Units
ns
ns
ns
ns
81
Revision 1.0
November 2004