K5L5628JTM Datasheet, PDF (36/98 Pages) Samsung semiconductor – 256M Bit (16M x16) Synchronous Burst , Multi Bank NOR Flash / 128M Bit(8M x16) Synchronous Burst UtRAM

K5L5628JT(B)M
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MCP MEMORY
DEVICE OPERATION
To write a command or command sequence (which includes programming data to the device and erasing blocks of memory), the sys-
tem must drive CLK, WE and CE to VIL and OE to VIH when providing address or data. The device provide the unlock bypass mode
to save its program time for program operation. Unlike the standard program command sequence which is comprised of four bus
cycles, only two program cycles are required to program a word in the unlock bypass mode. One block, multiple blocks, or the entire
device can be erased. Table 3 indicates the address space that each block occupies. The device’s address space is divided into six-
teen banks: Bank 0 contains the boot/parameter blocks, and the other banks(from Bank 1 to 15) consist of uniform blocks. A “bank
address” is the address bits required to uniquely select a bank. Similarly, a “block address” is the address bits required to uniquely
select a block. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The AC Character-
istics section contains timing specification tables and timing diagrams for write operations.
Read Mode
The device automatically enters to asynchronous read mode after device power-up. No commands are required to retrieve data in
asynchronous mode. After completing an Internal Program/Erase Routine, each bank is ready to read array data. The reset com-
mand is required to return a bank to the read(or erase-suspend-read)mode if DQ5 goes high during an active program/erase opera-
tion, or if the bank is in the autoselect mode.
The synchronous(burst) mode will automatically be enabled on the first rising edge on the CLK input while AVD is held low. That
means device enters burst read mode from asynchronous read mode to burst read mode using CLK and AVD signal. When the burst
read is finished(or terminated), the device return to asynchronous read mode automatically.
Asynchronous Read Mode
For the asynchronous read mode a valid address should be asserted on A0-A23, while driving AVD and CE to VIL. WE should
remain at VIH . The data will appear on DQ0-DQ15. Since the memory array is divided into sixteen banks, each bank remains
enabled for read access until the command register contents are altered.
Address access time (tAA) is equal to the delay from valid addresses to valid output data. The chip enable access time(tCE) is the
delay from the falling edge of CE to valid data at the outputs. The output enable access time(tOE) is the delay from the falling edge of
OE to valid data at the output. To prevent the memory content from spurious altering during power transition, the initial state machine
is set for reading array data upon device power-up, or after a hardware reset.
Synchronous (Burst) Read Mode
The device is capable of continuous linear burst operation and linear burst operation of a preset length. For the burst mode, the sys-
tem should determine how many clock cycles are desired for the initial word(tIACC) of each burst access and what mode of burst
operation is desired using "Burst Mode Configuration Register" command sequences. See "Set Burst Mode Configuration" for further
details. The status data also can be read during burst read mode by using AVD signal with a bank address. To initiate the synchro-
nous read again, a new address and AVD pulse is needed after the host has completed status reads or the device has completed
the program or erase operation.
Continuous Linear Burst Read
The synchronous(burst) mode will automatically be enabled on the first rising edge on the CLK input while AVD is held low. Note that
the device is enabled for asynchronous mode when it first powers up. The initial word is output tIAA after the rising edge of the first
CLK cycle. Subsequent words are output tBA after the rising edge of each successive clock cycle, which automatically increments the
internal address counter. Note that the device has internal address boundary that occurs every 16 words. When the device is cross-
ing the first word boundary, additional clock cycles are needed before data appears for the next address. The number of addtional
clock cycle can varies from zero to three cycles, and the exact number of additional clock cycle depends on the starting address of
burst read.(Refer to Figure 13) The RDY output indicates this condition to the system by pulsing low. The device will continue to out-
put sequential burst data, wrapping around to address 000000h after it reaches the highest addressable memory location until the
system asserts CE high, RESET low or AVD low in conjunction with a new address.(See Table 4.) The reset command does not ter-
minate the burst read operation.
If the host system crosses the bank boundary while reading in burst mode, and the accessed bank is not programming or erasing, a
additional clock cycles are needed as previously mentioned. If the host system crosses the bank boundary while the accessed bank
is programming or erasing, that is busy bank, the synchronous read will be terminated.
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Revision 1.0
November 2004