K5L5628JTM Datasheet, PDF (67/98 Pages) Samsung semiconductor – 256M Bit (16M x16) Synchronous Burst , Multi Bank NOR Flash / 128M Bit(8M x16) Synchronous Burst UtRAM

K5L5628JT(B)M
PPrreelliimmiinnaarryy
MCP MEMORY
FUNCTIONAL DESCRIPTION
Table 3. ASYNCHRONOUS 4 PAGE READ & ASYNCHRONOUS WRITE MODE(A15/A14=0/0)
CS
MRS
OE
WE
LB
UB
H
H
X¹⁾
X¹⁾
X¹⁾
X¹⁾
H
L
X¹⁾
X¹⁾
X¹⁾
X¹⁾
L
H
H
H
X¹⁾
X¹⁾
L
H
X¹⁾
X¹⁾
H
H
L
H
L
H
L
H
L
H
L
H
H
L
L
H
L
H
L
L
L
H
H
L
L
H
L
H
H
L
H
L
L
H
H
L
L
L
L
L
H
L
L
L
1. X must be low or high state.
2. In asynchronous mode, Clock and ADV are ignored.
3. /WAIT pin is High-Z in Asynchronous mode.
DQ0~7
High-Z
High-Z
High-Z
High-Z
Dout
High-Z
Dout
Din
High-Z
Din
High-Z
DQ8~15
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
Dout
High-Z
Din
Din
High-Z
Mode
Deselected
Deselected
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
Lower Byte Write
Upper Byte Write
Word Write
Mode Register Set
Power
Standby
PAR
Active
Active
Active
Active
Active
Active
Active
Active
Active
Table 5. SYNCHRONOUS BURST READ & SYNCHRONOUS BURST WRITE MODE(A15/A14=1/0)
CS MRS OE WE LB UB DQ0~7 DQ8~15 CLK
ADV
Mode
Power
H
H
X¹⁾
X¹⁾
X¹⁾ X¹⁾ High-Z High-Z
X²⁾
X²⁾
Deselected
Standby
H
L
X¹⁾
X¹⁾
X¹⁾ X¹⁾ High-Z High-Z
X²⁾
X²⁾
Deselected
PAR
L
H
H
H
X¹⁾ X¹⁾ High-Z High-Z
X²⁾
H
Output Disabled
Active
L
H
X¹⁾
X¹⁾
H
H High-Z High-Z
X²⁾
H
Output Disabled
Active
L
H
X¹⁾
H
X¹⁾ X¹⁾ High-Z High-Z
Read Command
Active
L
H
L
H
L
H
Dout High-Z
H
Lower Byte Read
Active
L
H
L
H
H
L High-Z Dout
H
Upper Byte Read
Active
L
H
L
H
L
L
Dout
Dout
H
Word Read
Active
L
H
X¹⁾
L or
X¹⁾
X¹⁾ High-Z High-Z
Write Command
Active
L
H
H
X¹⁾
L
H
Din High-Z
H
Lower Byte Write
Active
L
H
H
X¹⁾
H
L High-Z Din
H
Upper Byte Write
Active
L
H
H
X¹⁾
L
L
Din
Din
H
Word Write
Active
L
L
H L or
L
L High-Z High-Z
Mode Register Set
Active
1. X must be low or high state.
2. X means "Don’t care"(can be low, high or toggling).
3. /WAIT is device output signal so does not have any affect to the mode definition. Please refer to each timing diagram for /WAIT pin function.
4. The last data written in the previous Asynchronous write mode is not valid. To make the lastly written data valid, then implement at least one dummy
write cycle before change mode into synchronous burst read and synchronous burst write mode.
5. The data written in Synchronous burst write operation can be corrupted by the next Asynchronous write operation. So the transition from Synchronous
burst write operation to Asynchronous write operation is prohibited.
67
Revision 1.0
November 2004