K5L5628JTM Datasheet, PDF (62/98 Pages) Samsung semiconductor – 256M Bit (16M x16) Synchronous Burst , Multi Bank NOR Flash / 128M Bit(8M x16) Synchronous Burst UtRAM

K5L5628JT(B)M
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MCP MEMORY
Crossing of First Word Boundary in Burst Read Mode
The additional clock insertion for word boundary is needed only at the first crossing of word boundary. This means that no addtional
clock cycle is needed from 2nd word boundary crossing to the end of continuous burst read. Also, the number of addtional clock cycle
for the first word boundary can varies from zero to three cycles, and the exact number of additional clock cycle depends on the start-
ing address of burst read.
The rule to determine the additional clock cycle is as follows. All addresses can be divided into 4 groups. The applied rule is "The res-
idue obtained when the address is divided by 4" or "two LSB bits of address". Using this rule, all address can be divided by 4 different
groups as shown in below table. For simplicity of terminology, "4N" stands for the address of which the residue is "0"(or the two LSB
bits are "00") and "4N+1" for the address of which the residue is "1"(or the two LSB bits are "01"), etc.
The additional clock cycles for first word boundary crossing are zero, one, two or three when the burst read start from "4N" address,
"4N+1" address, "4N+2" address or "4N+3" address respectively.
Starting Address vs. Additional Clock Cycles for first word boundary
Srarting Address Group
for Burst Read
The Residue of (Address/4)
LSB Bits of Address
4N
0
00
4N+1
1
01
4N+2
2
10
4N+3
3
11
Additional Clock Cycles for
First Word Boundary Crossing
0 cycle
1 cycle
2 cycles
3 cycles
Case 1 : Start from "4N" address group
A0-A23
Data Bus
5 cycle for initial access shown.(54MHz case)
C
D
E
F
10
11
12
13
CLK
C
AVD
D
E
F
10
11
12
13
14
No Additional Cycle for First Word Boundary
CE
tCEZ
OE
tOER
tOEZ
RDY
Notes:
1. Address boundry occurs every 16 words beginning at address 00000FH , 00001FH , 00002FH , etc.
2. Address 000000H is also a boundry crossing.
3. No additional clock cycles are needed except for 1st boundary crossing.
Figure 16. Crossing of first word boundary in burst read mode.
62
Revision 1.0
November 2004