K5L5628JTM Datasheet, PDF (77/98 Pages) Samsung semiconductor – 256M Bit (16M x16) Synchronous Burst , Multi Bank NOR Flash / 128M Bit(8M x16) Synchronous Burst UtRAM

K5L5628JT(B)M
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Test Input/Output Reference)
Input pulse level: 0.2 to VCCQ-0.2V
Input rising and falling time: 3ns
Input and output reference voltage: 0.5 x VCCQ
Output load: CL=30pF
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MCP MEMORY
Figure 14. AC Output Load Circuit
Vtt=0.5 x VCCQ
Dout
Z0=50Ω
50Ω
30pF
Table 18. ASYNCHRONOUS AC CHARACTERISTICS (VCC=2.5~2.7V, VCCQ=1.7~2.0V, TA=-30 to 85°C)
Parameter List
Common CS High Pulse Width
Read Cycle Time
Page Read Cycle Time
Address Access Time
Page Access Time
Chip Select to Output
Async.
(Page)
Read
Output Enable to Valid Output
UB, LB Access Time
Chip Select to Low-Z Output
UB, LB Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
UB, LB Disable to High-Z Output
Output Disable to High-Z Output
Output Hold
Write Cycle Time
Chip Select to End of Write
ADV Minimum Low Pulse Width
Address Set-up Time to Beginning of Write
Async.
Write
Address Valid to End of Write
UB, LB Valid to End of Write
Write Pulse Width
WE High Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from Write Time
1. tWP(min)=70ns for continuous write operation over 50 times.
Symbol
tCSHP(A)
tRC
tPC
tAA
tPA
tCO
tOE
tBA
tLZ
tBLZ
tOLZ
tCHZ
tBHZ
tOHZ
tOH
tWC
tCW
tADV
tAS
tAW
tBW
tWP
tWHP
tWR
tDW
tDH
Speed
Min
Max
10
-
70
-
25
-
-
70
-
20
-
70
-
35
-
35
10
-
5
-
5
-
0
12
0
12
0
12
3
-
70
-
60
-
7
-
0
-
60
-
60
-
55¹⁾
-
5
-
0
-
30
-
0
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
77
Revision 1.0
November 2004