K5L5628JTM Datasheet, PDF (95/98 Pages) Samsung semiconductor – 256M Bit (16M x16) Synchronous Burst , Multi Bank NOR Flash / 128M Bit(8M x16) Synchronous Burst UtRAM

K5L5628JT(B)M
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MCP MEMORY
TRANSITION TIMING WAVEFORM BETWEEN READ AND WRITE
Fig.37 ASYNCH. WRITE(Low ADV Type) to SYNCH. BURST READ TIMING WAVEFORM
[Latency=5, Burst Length=4](MRS=VIH)
CLK
ADV
Address
CS
WE
OE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
T
tWC
Valid
tAW
tCW
tWLRL
tWP
tAD^tHAPDVS
tADVH
tAS(B)
tAH(B)
Valid
Don’t Care
tWR
tCSS(B)
tBC
tAS
tOEL
LB, UB
Data in
Data out
tBW
tDW tDH
Data Valid
High-Z
tBEL
Latency 5
tCD
tOH
tHZ
DQ0 DQ1 DQ2 DQ3
WAIT
tWL
tWH
tWZ
High-Z
Read Latency 5
(SYNCHRONOUS BURST READ CYCLE)
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
should be met.
2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
/WAIT High(tWH) : Data available(driven by Latency-1 clock)
/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)
3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
4. Burst Cycle Time(tBC) should not be over 2.5µs.
(LOW ADV TYPE ASYNCHRONOUS WRITE CYCLE - WE controlled)
1. Clock input does not have any affect to the write operation if WE is driven to low before Read Latency-1 clock. Read Latency-1 clock
in write timing is just a reference to WE low going for proper write operation.
Table 41. ASYNCH. WRITE(Low ADV Type) to BURST READ AC CHARACTERISTICS
Symbol
tWLRL
Speed
Min
Max
1
-
Units
clock
Symbol
tADHP
Speed
Min
Max
5
-
Units
ns
95
Revision 1.0
November 2004