K5L5628JTM Datasheet, PDF (49/98 Pages) Samsung semiconductor – 256M Bit (16M x16) Synchronous Burst , Multi Bank NOR Flash / 128M Bit(8M x16) Synchronous Burst UtRAM

K5L5628JT(B)M
PPrreelliimmiinnaarryy
MCP MEMORY
SWITCHING WAVEFORMS
5 cycles for initial access shown.
CR setting : A14=0, A13=0, A12=1
tCES
CE
15.2 ns typ.
CLK
tAVDS
AVD
A0-A23
tAVDH
tACS
tACH
DQ0-DQ15
tIAA
tBDH
tBA
D6
D7 D0 D1
D2 D3
D7 D0
OE
Hi-Z
RDY
tOER
tRDYA
tRDYS
Figure 5. 8 word Linear Burst Mode with Wrap Around (66 MHz)
Note: In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high.
5 cycles for initial access shown.
CR setting : A14=0, A13=0, A12=1
tCES
CE
15.2 ns typ.(66MHz)
CLK
tAVDS
AVD
A0-A23
tAVDH
tACS
tACH
DQ0-DQ15
tIAA
tBDH
tBA
D6
D7 D0 D1
D2 D3
D7 D0
OE
Hi-Z
RDY
tOER
tRDYA
tRDYS
Figure 6. 8 word Linear Burst with RDY Set One Cycle Before Data (CR setting : A18=1)
Note: In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high.
49
Revision 1.0
November 2004