K5L5628JTM Datasheet, PDF (40/98 Pages) Samsung semiconductor – 256M Bit (16M x16) Synchronous Burst , Multi Bank NOR Flash / 128M Bit(8M x16) Synchronous Burst UtRAM

K5L5628JT(B)M
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MCP MEMORY
Single word accelerated program operation
The system would use two-cycle program sequence (One-cycle (XXX - A0H) is for single word program command, and Next one-
cycle (PA - PD) is for program address and data ).
Quadruple word accelerated program operation
As well as Single word accelerated program, the system would use five-cycle program sequence (One-cycle (XXX - A5H) is for qua-
druple word program command, and four cycles are for program address and data).
• Only four words programming is possible
• Each program address must have the same A23~A2 address
• The device automatically generates adequate program pulses and ignores other command after program command
Unlock Bypass
The device provides the unlock bypass mode to save its operation time. This mode is possible for program, block erase and chip
erase operation. There are two methods to enter the unlock bypass mode. The mode is invoked by the unlock bypass command
sequence or the assertion of VID on VPP pin. Unlike the standard program/erase command sequence that contains four/six bus
cycles, the unlock bypass program/erase command sequence needs only two bus cycles. The unlock bypass mode is engaged by
issuing the unlock bypass command sequence which is comprised of three bus cycles. Writing first two unlock cycles is followed by
a third cycle containing the unlock bypass command (20H). Once the device is in the unlock bypass mode, the unlock bypass pro-
gram/erase command sequence is necessary. The unlock bypass program command sequence is comprised of only two bus cycles;
writing the unlock bypass program command (A0H) is followed by the program address and data. This command sequence is the
only valid one for programming the device in the unlock bypass mode. Also, The unlock bypass erase command sequence is com-
prised of two bus cycles; writing the unlock bypass block erase command(80H-30H) or writing the unlock bypass chip erase com-
mand(80H-10H). This command sequences are the only valid ones for erasing the device in the unlock bypass mode. The unlock
bypass reset command sequence is the only valid command sequence to exit the unlock bypass mode. The unlock bypass reset
command sequence consists of two bus cycles. The first cycle must contain the data (90H). The second cycle contains only the data
(00H). Then, the device returns to the read mode.
To enter the unlock bypass mode in hardware level, the VID also can be used. By assertion VID on the VPP pin, the device enters the
unlock bypass mode. Also, the all blocks are temporarily unprotected when the device using the VID for unlock bypass mode. To exit
the unlock bypass mode, just remove the asserted VID from the VPP pin.(Note that user never float the Vpp, that is, Vpp is always
connected with VIH, VIL or VID.).
Chip Erase
To erase a chip is to write 1′s into the entire memory array by executing the Internal Erase Routine. The Chip Erase requires six bus
cycles to write the command sequence. The erase set-up command is written after first two "unlock" cycles. Then, there are two
more write cycles prior to writing the chip erase command. The Internal Erase Routine automatically pre-programs and verifies the
entire memory for an all zero data pattern prior to erasing. The automatic erase begins on the rising edge of the last WE pulse in the
command sequence and terminates when DQ7 is "1". After that the device returns to the read mode.
Block Erase
To erase a block is to write 1′s into the desired memory block by executing the Internal Erase Routine. The Block Erase requires six
bus cycles to write the command sequence shown in Table 5. After the first two "unlock" cycles, the erase setup command (80H) is
written at the third cycle. Then there are two more "unlock" cycles followed by the Block Erase command. The Internal Erase Routine
automatically pre-programs and verifies the entire memory prior to erasing it. Multiple blocks can be erased sequentially by writing
the sixth bus-cycle. Upon completion of the last cycle for the Block Erase, additional block address and the Block Erase command
(30H) can be written to perform the Multi-Block Erase. For the Multi-Block Erase, only sixth cycle(block address and 30H) is
needed.(Similarly, only second cycle is needed in unlock bypass block erase.) An 50us (typical) "time window" is required between
the Block Erase command writes. The Block Erase command must be written within the 50us "time window", otherwise the Block
Erase command will be ignored. The 50us "time window" is reset when the falling edge of the WE occurs within the 50us of "time
window" to latch the Block Erase command. During the 50us of "time window", any command other than the Block Erase or the
Erase Suspend command written to the device will reset the device to read mode. After the 50 us of "time window", the Block Erase
command will initiate the Internal Erase Routine to erase the selected blocks. Any Block Erase address and command following the
exceeded "time window" may or may not be accepted. No other commands will be recognized except the Erase Suspend command
during Block Erase operation.
The device provides accelerated erase operations through the Vpp input. When VID is asserted on the Vpp input, the device auto-
matically enters the Unlock Bypass mode, temporarily unprotects any protected blocks, and uses the higher voltage on the input to
reduce the time required for erase. By removing VID returns the device to normal operation mode.
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Revision 1.0
November 2004