K5L5628JTM Datasheet, PDF (66/98 Pages) Samsung semiconductor – 256M Bit (16M x16) Synchronous Burst , Multi Bank NOR Flash / 128M Bit(8M x16) Synchronous Burst UtRAM

K5L5628JT(B)M
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MCP MEMORY
POWER UP SEQUENCE
After applying VCC upto minimum operating voltage(2.5V), drive CS High first and then drive MRS High. Then the device gets into the
Power Up mode. Wait for minimum 200µs to get into the normal operation mode. During the Power Up mode, the standby current can
not be guaranteed. To get the stable standby current level, at least one cycle of active operation should be implemented regardless of
wait time duration. To get the appropriate device operation, be sure to keep the following power up sequence.
1. Apply power.
2. Maintain stable power(Vcc min.=2.5V) for a minimum 200µs with CS and MRS high.
Fig.3 POWER UP TIMING
VCC(Min)
VCC
VCCQ(Min)
VCCQ
MRS
CS
200µs
Min. 0ns
Min. 0ns
Min. 200µs
Power Up Mode
Normal Operation
Fig.4 STANDBY MODE STATE MACHINES
Power On
CS=VIH
MRS=VIH
Initial State
(Wait 200µs)
CS=UB=LB=VIL,
WE=VIL, MRS=VIL
MRS Setting
CS=VIL, UB or LB=VIL
MRS=VIH
Active
CS=VIH
Standby
Mode
MRS=VIH
MRS=VIL
PAR
Mode
MRS Setting
CS=VIL,
WE=VIL, MRS=VIL
Default mode after power up is Asynchronous mode(4 Page Read and Asynchronous Write). But this default mode is not 100%
guaranteed so MRS setting sequence is highly recommended after power up.
For entry to PAR mode, drive MRS pin into VIL for over 0.5µs(suspend period) during standby mode after MRS setting has
been completed(A4=1, A3=0). If MRS pin is driven into VIH during PAR mode, the device gets back to the standby mode
without wake up sequence.
66
Revision 1.0
November 2004