K5L5628JTM Datasheet, PDF (74/98 Pages) Samsung semiconductor – 256M Bit (16M x16) Synchronous Burst , Multi Bank NOR Flash / 128M Bit(8M x16) Synchronous Burst UtRAM

K5L5628JT(B)M
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MCP MEMORY
LOW POWER FEATURES
Internal TCSR
The internal Temperature Compensated Self Refresh(TCSR)
feature is a very useful tool for reducing standby current in room
temperature(below 40°C). DRAM cell has weak refresh charac-
teristics in higher temperature. So high temperature requires
more refresh cycles, which lead to standby current increase.
Without internal TCSR, the refresh cycle should be set as worst
condition so as to cover high temperature(85°C) refresh char-
acteristics. But with internal TCSR, the refresh cycle below
40°C can be optimized, so the standby current in room temper-
ature can be highly reduced. This feature is really beneficial to
mobile phone because most of mobile phones are used at
below 40°C in the phone standby mode.
Fig.13 PAR MODE EXECUTION and EXIT
MRS
MODE
Normal
Operation
0.5µs
Suspend
PAR mode
Normal
Operation
Driver Strength Optimization
The optimization of output driver strength is possible through
the mode register setting to adjust for the different data load-
ings. Through this driver strength optimization, the device can
minimize the noise generated on the data bus during read oper-
ation. The device supports full drive, 1/2 drive and 1/4 drive.
Partial Array Refresh(PAR) mode
The PAR mode enables the user to specify the active memory
array size. UtRAM consists of 4 blocks and user can select
1 block, 2 blocks, 3 blocks or all blocks as active memory array
through Mode Register Setting. The active memory array is
periodically refreshed whereas the disabled array is not going
to be refreshed and so the previously stored data will get lost.
Even though PAR mode is enabled through the Mode Register
Setting, PAR mode execution by MRS pin is still needed.
The normal operation can be executed even in refresh-disabled
array as long as MRS pin is not driven to low for over 0.5µs.
Driving MRS pin to high makes the device to get back to the
normal operation mode from PAR executed mode,
Refer to Fig.13 and Table 12 for PAR operation and PAR
address mapping.
CS
Table 12. PAR MODE CHARACTERISTIC
Power Mode
Address
(Bottom Array)²⁾
Address
(Top Array)²⁾
Memory Standby³⁾ Standby³⁾
Wait
Cell Data (ISB1, <40°C) (ISB1, <85°C) Time(µs)
Standby(Full Array)
000000h ~ 7FFFFFh 000000h ~ 7FFFFFh _Valid¹⁾
130µA
250µA
0
Partial Refresh(3/4 Block) 000000h ~ 5FFFFFh 200000h ~ 7FFFFFh _Valid¹⁾
125µA
235µA
0
Partial Refresh(1/2 Block) 000000h ~ 3FFFFFh 400000h ~ 7FFFFFh _Valid¹⁾
120µA
220µA
0
Partial Refresh(1/4 Block) 000000h ~ 1FFFFFh 600000h ~ 7FFFFFh _Valid¹⁾
115µA
205µA
0
1. Only the data in the refreshed block are valid
2. PAR Array can be selected through Mode Register Set(See Page 66)
3. Standby mode is supposed to be set up after at least one active operation.after power up.
ISB1 is measured after 60ms from the time when standby mode is set up.
74
Revision 1.0
November 2004