K5L5628JTM Datasheet, PDF (39/98 Pages) Samsung semiconductor – 256M Bit (16M x16) Synchronous Burst , Multi Bank NOR Flash / 128M Bit(8M x16) Synchronous Burst UtRAM

K5L5628JT(B)M
PPrreelliimmiinnaarryy
MCP MEMORY
Output Disable Mode
When the OE input is at VIH , output from the device is disabled. The outputs are placed in the high impedance state.
Block Protection & Unprotection
To protect the block from accidental writes, the block protection/unprotection command sequence is used. On power up, all blocks in
the device are protected. To unprotect a block, the system must write the block protection/unprotection command sequence. The first
two cycles are written: addresses are don’t care and data is 60h. Using the third cycle, the block address (ABP) and command (60h)
is written, while specifying with addresses A6, A1 and A0 whether that block should be protected (A6 = VIL, A1 = VIH, A0 = VIL) or
unprotected (A6 = VIH, A1 = VIH, A0 = VIL). After the third cycle, the system can continue to protect or unprotect additional cycles, or
exit the sequence by writing F0h (reset command).
The device offers three types of data protection at the block level:
• The block protection/unprotection command sequence disables or re-enables both program and erase operations in any block.
• When WP is at VIL, the two outermost blocks are protected.
• When VPP is at VIL, all blocks are protected.
Note that user never float the Vpp and WP, that is, Vpp is always connected with VIH, VIL or VID and WP is VIH or VIL.
Hardware Reset
The device features a hardware method of resetting the device by the RESET input. When the RESET pin is held low(VIL) for at least
a period of tRP, the device immediately terminates any operation in progress, tristates all outputs, and ignores all read/write com-
mands for the duration of the RESET pulse. The device also resets the internal state machine to asynchronous read mode. To
ensure data integrity, the interrupted operation should be reinitiated once the device is ready to accept another command sequence.
As previously noted, when RESET is held at VSS ± 0.2V, the device enters standby mode. The RESET pin may be tied to the system
reset pin. If a system reset occurs during the Internal Program or Erase Routine, the device will be automatically reset to the asyn-
chronous read mode; this will enable the systems microprocessor to read the boot-up firmware from the Flash memory. If RESET is
asserted during a program or erase operation, the device requires a time of tREADY (during Internal Routines) before the device is
ready to read data again. If RESET is asserted when a program or erase operation is not executing, the reset operation is completed
within a time of tREADY (not during Internal Routines). tRH is needed to read data after RESET returns to VIH. Refer to the AC Char-
acteristics tables for RESET parameters and to Figure 6 for the timing diagram.
Software Reset
The reset command provides that the bank is reseted to read mode, erase-suspend-read mode or program-suspend-read mode. The
addresses are in Don’t Care state. The reset command may be written between the sequence cycles in an erase command
sequence before erasing begins, or in a program command sequence before programming begins. If the device begins erasure or
programming, the reset command is ignored until the operation is completed. If the program command sequence is written to a bank
that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. The reset com-
mand is valid between the sequence cycles in an autoselect command sequence. In an autoselect mode, the reset command must
be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset com-
mand returns that bank to the erase-suspend-read mode. Also, if a bank entered the autoselect mode while in the Program Suspend
mode, writing the reset command returns that bank to the program-suspend-read mode. If DQ5 goes high during a program or an
erase operation, writing the reset command returns the banks to the read mode. (or erase-suspend-read mode if the bank was in
Erase Suspend)
Program
The device can be programmed in units of a word. Programming is writing 0's into the memory array by executing the Internal Pro-
gram Routine. In order to perform the Internal Program Routine, a four-cycle command sequence is necessary. The first two cycles
are unlock cycles. The third cycle is assigned for the program setup command. In the last cycle, the address of the memory location
and the data to be programmed at that location are written. The device automatically generates adequate program pulses and veri-
fies the programmed cell margin by the Internal Program Routine. During the execution of the Routine, the system is not required to
provide further controls or timings. During the Internal Program Routine, commands written to the device will be ignored.
Note that a hardware reset during a program operation will cause data corruption at the corresponding location.
Accelerated Program Operation
The device provides Single/Quadruple word accelerated program operations through the Vpp input. Using this mode, faster manu-
facturing throughput at the factory is possible. When VID is asserted on the Vpp input, the device automatically enters the Unlock
Bypass mode, temporarily unprotects any protected blocks, and uses the higher voltage on the input to reduce the time required for
program operations. By removing VID returns the device to normal operation mode.
Note that Read while Accelerated Programm and Program suspend mode are not guaranteed
39
Revision 1.0
November 2004