K5L5628JTM Datasheet, PDF (47/98 Pages) Samsung semiconductor – 256M Bit (16M x16) Synchronous Burst , Multi Bank NOR Flash / 128M Bit(8M x16) Synchronous Burst UtRAM

K5L5628JT(B)M
PPrreelliimmiinnaarryy
MCP MEMORY
CAPACITANCE(TA = 25 °C, VCC = 1.8V, f = 1.0MHz)
Item
Symbol
Test Condition
Min
Input Capacitance
CIN
VIN=0V
-
Output Capacitance
Control Pin Capacitance
COUT
VOUT=0V
-
CIN2
VIN=0V
-
Note : Capacitance is periodically sampled and not 100% tested.
Max
10
10
10
Unit
pF
pF
pF
AC TEST CONDITION
Parameter
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
Value
0V to VCC
5ns
VCC/2
CL = 30pF
VCC
0V
VCC/2
Input & Output
Test Point
VCC/2
Input Pulse and Test Point
AC CHARACTERISTICS
Synchronous/Burst Read
Parameter
Symbol
Initial Access Time
Burst Access Time Valid Clock to Output Delay
AVD Setup Time to CLK
AVD Hold Time from CLK
AVD High to OE Low
Address Setup Time to CLK
Address Hold Time from CLK
Data Hold Time from Next Clock Cycle
Output Enable to Data
Output Enable to RDY valid
CE Disable to High Z
OE Disable to High Z
CE Setup Time to CLK
CLK to RDY Setup Time
RDY Setup Time to CLK
CLK High or Low Time
CLK Fall or Rise Time
tIAA
tBA
tAVDS
tAVDH
tAVDO
tACS
tACH
tBDH
tOE
tOER
tCEZ
tOEZ
tCES
tRDYA
tRDYS
tCH/L
tCHCL
Device
Under
Test
* CL = 30pF including scope
and Jig capacitance
Output Load
7B
(54 MHz)
Min
Max
-
88.5
-
14.5
5
-
7
-
0
-
5
-
7
-
4
-
-
20
-
14.5
-
20
-
15
7
-
-
14.5
4
-
4.5
-
-
3
7C
(66 MHz)
Unit
Min
Max
-
70
ns
-
11
ns
5
-
ns
6
-
ns
0
-
ns
5
-
ns
6
-
ns
4
-
ns
-
20
ns
-
11
ns
-
20
ns
-
15
ns
6
-
ns
-
11
ns
4
-
ns
3.5
-
ns
-
3
ns
47
Revision 1.0
November 2004