K5L5628JTM Datasheet, PDF (90/98 Pages) Samsung semiconductor – 256M Bit (16M x16) Synchronous Burst , Multi Bank NOR Flash / 128M Bit(8M x16) Synchronous Burst UtRAM

K5L5628JT(B)M
PPrreelliimmiinnaarryy
MCP MEMORY
SYNCHRONOUS BURST WRITE STOP TIMING WAVEFORM
Fig.32 TIMING WAVEFORM OF BURST WRITE STOP by CS [Latency=5,Burst Length=4,WP=Low enable](OE=VIH, MRS=VIH)
CLK
ADV
Address
CS
LB, UB
WE
Data in
WAIT
0
1
2
3
4
5
6
7
8
9 10 11 12 13
T
tADVH
tADVS
tAS(B)
Valid
tAH(B)
Don’t Care
tCSS(B)
tBS
tBSADV
Valid
tCSHP
tCSLH
tBH
tWEH
tWES
tWL
High-Z
Latency 5
tWH
tWHP
tDS
D0
tDHC
D1
tWZ
tWL
High-Z
Latency 5
tWH
D0 D1 D2
(SYNCHRONOUS BURST WRITE STOP TIMING)
1. The new burst operation can be issued only after the previous burst operation is finished.
2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
/WAIT High(tWH) : Data available(driven by Latency-1 clock)
/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)
3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
4. The burst stop operation should not be repeated for over 2.5µs.
Table 36. BURST WRITE STOP AC CHARACTERISTICS
Symbol
tBSADV
tCSLH
tCSHP
tBS
tBH
tWES
tWEH
Speed
Min
Max
12
-
7
-
5
-
5
-
5
-
5
-
5
-
Units
ns
ns
ns
ns
ns
ns
ns
Symbol
tWHP
tDS
tDHC
tWL
tWH
tWZ
Speed
Min
Max
5
-
5
-
3
-
-
10
-
12
-
12
Units
ns
ns
ns
ns
ns
ns
90
Revision 1.0
November 2004