K5L5628JTM Datasheet, PDF (37/98 Pages) Samsung semiconductor – 256M Bit (16M x16) Synchronous Burst , Multi Bank NOR Flash / 128M Bit(8M x16) Synchronous Burst UtRAM

K5L5628JT(B)M
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MCP MEMORY
8-,16-Word Linear Burst Read
As well as the Continuous Linear Burst Mode, there are two(8 & 16 word) linear wrap & no-wrap mode, in which a fixed number of
words are read from consecutive addresses. In these modes, the addresses for burst read are determined by the group within which
the starting address falls. The groups are sized according to the number of words read in a single burst sequence for a given
mode.(See Table. 6)
Table 6. Burst Address Groups(Wrap mode only)
Burst Mode
Group Size
Group Address Ranges
8 word
8 words
0-7h, 8-Fh, 10-17h, ....
16 word
16words
0-Fh, 10-1Fh, 20-2Fh, ....
As an example:
In wrap mode case, if the starting address in the 8-word mode is 2h, the address range to be read would be 0-7h, and the wrap burst
sequence would be 2-3-4-5-6-7-0-1h. The burst sequence begins with the starting address written to the device, but wraps back to
the first address in the selected group. In a similar manner, 16-word wrap mode begin their burst sequence on the starting address
written to the device, and then wrap back to the first address in the selected address group.
In no-wrap mode case, if the starting address in the 8-word mode is 2h, the no-wrap burst sequence would be 2-3-4-5-6-7-8-9h. The
burst sequence begins with the starting address written to the device, and continue to the 8th address from starting address. In a sim-
ilar manner, 16-word no-wrap mode begin their burst sequence on the starting address written to the device, and continue to the 16th
address from starting address. Also, when the address cross the word boundary in no-wrap mode, same number of additional clock
cycles as continuous linear mode is needed.
Programmable Wait State
The programmable wait state feature indicates to the device the number of additional clock cycles that must elapse after AVD is
driven active for burst read mode. Upon power up, the number of total initial access cycles defaults to seven.
Handshaking
The handshaking feature allows the host system to simply monitor the RDY signal from the device to determine when the initial word
of burst data is ready to be read. To set the number of initial cycle for optimal burst mode, the host should use the programmable wait
state configuration.(See "Set Burst Mode Configuration Register" for details.) The rising edge of RDY after OE goes low indicates
the initial word of valid burst data. Using the autoselect command sequence the handshaking feature may be verified in the device.
Set Burst Mode Configuration Register
The device uses a configuration register to set the various burst parameters : the number of initial cycles for burst and burst read
mode. The burst mode configuration register must be set before the device enter burst mode.
The burst mode configuration register is loaded with a three-cycle command sequences. On the third cycle, the data should be C0h,
address bits A11-A0 should be 555h, and address bits A18-A12 set the code to be latched. The device will power up or after a hard-
ware reset with the default setting.
Table 7. Burst Mode Configuration Register Table
Address Bit
Function
Settings(Binary)
A18
RDY Active
1 = RDY active one clock cycle before data
0 = RDY active with data(default)
A17
000 = Continuous(default)
001 = 8-word linear with wrap
A16
Burst Read Mode
010 = 16-word linear with wrap
011 = 8-word linear with no-wrap
A15
100 = 16-word linear with no-wrap
101 ~ 111 = Reserve
A14
000 = Data is valid on the 4th active CLK edge after AVD transition to VIH
001 = Data is valid on the 5th active CLK edge after AVD transition to VIH
A13
010 = Data is valid on the 6th active CLK edge after AVD transition to VIH
Programmable Wait State
011 = Data is valid on the 7th active CLK edge after AVD transition to VIH (default)
100 = Reserve
A12
101 = Reserve
110 = Reserve
111 = Reserve
Programmable Wait State Configuration
This feature informs the device of the number of clock cycles that must elapse after AVD# is driven active before data will be avail-
able. This value is determined by the input frequency of the device. Address bits A14-A12 determine the setting. (See Burst Mode
Configuration Register Table)
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Revision 1.0
November 2004