E702289_SH7290 Datasheet, PDF (240/252 Pages) Renesas Technology Corp – SH7290 E10A Emulator

Table 6.12 Measurement Item (cont)
Selected Name
X/Y-RAM access stall
URAM access stall
Instruction/data access stall cycle
Other access cycles than instruction/data
Non-cacheable area access cycle
Non-cacheable area instruction access cycle
Non-cacheable area data access cycle
Cacheable area access cycle
Cacheable area instruction access cycle
Cacheable area data access cycle
Access counts other than instruction/data
Non-cacheable area access counts
Non-cacheable area instruction access counts
Non-cacheable area data access counts
Cacheable area access counts
Cacheable area instruction access counts
Cacheable area data access counts
Option
XYS
US
MA
NMA
NCC
NCI
NCD
CC
CIC
CDC
NAM
NCN
NCIN
NCDN
CN
CIN
CDN
Each measurement condition is also counted when conditions in table 6.13 are generated.
Table 6.13 Performance Measurement Conditions to be Counted
Measurement Condition
No caching due to the
settings of TLB cacheable
bit
Cache-on counting
Branch count
Notes
Counted for accessing the cacheable area.
Accessing the non-cacheable area is counted less than the actual
number of cycles and counts. Accessing the cacheable, X/Y RAM,
and U RAM areas is counted more than the actual number of cycles
and counts.
The counter value is incremented by 2. This means that two cycles
are valid for one branch.
Notes: 1. In the non realtime trace mode of the AUD trace, normal counting cannot be
performed because the generation state of the stall or the execution cycle is changed.
2. Since the clock source of the counter is the CPU clock, counting also stops when the
clock halts in the sleep mode.
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