E702289_SH7290 Datasheet, PDF (225/252 Pages) Renesas Technology Corp – SH7290 E10A Emulator

6.5.2 Break Condition Functions
In addition to BREAKPOINT functions, the emulator has Break Condition functions. In the HDI,
three types of conditions can be set under Break Condition 1, 2, 3. Table 6.5 lists these conditions
of Break Condition.
Table 6.5 Types of Break Conditions
Break Condition Type
Description
Address bus condition (Address)
Breaks when the SH7290 address bus value or the program
counter value matches the specified value.
Data bus condition (Data)
Breaks when the SH7290 data bus value matches the
specified value. Byte, word, or longword can be specified as
the access data size and X-Bus or Y-Bus as the data type.
X-Bus or Y-Bus condition (Address Breaks when the X-Bus or Y-Bus address bus or data bus
and data)
matches the specified value.
Bus state condition
(Bus State)
There are two bus state condition settings:
Read/Write condition: Breaks when the SH7290 RD or
RDWR signal level matches the specified condition.
Bus state condition: Breaks when the operating state in an
SH7290 bus cycle matches the specified condition.
Types of buses that can be specified are listed below.
• L-bus (CPU-ALL): Indicates an instruction fetch and
data access, including a hit to the cache memory.
• L-bus (CPU-Data): Indicates a data access by the CPU,
including a hit to the cache memory.
• I-bus (CPU.DMA): Indicates a CPU cycle when the
cache memory is not hit, and a data access by the
DMA.
Internal I/O break condition
Breaks when the SH7290 accesses the internal I/O.
LDTLB instruction break condition Breaks when the SH7290 executes the LDTLB instruction.
Count
Breaks when the conditions set are satisfied the specified
number of times.
Note: When U-RAM or X/Y-RAM is accessed from the P0 space, the I-bus must be selected, and
when accessed from the P2 space, the L-bus must be selected. When cache fill cycle is
acquired, the I-bus must be selected.
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