PIC18F1220_07 Datasheet, PDF (91/308 Pages) Microchip Technology – 18/20/28-Pin High-Performance, Enhanced Flash Microcontrollers with 10-bit A/D and nanoWatt Technology

PIC18F1220/1320
FIGURE 10-6:
MCLR/VPP/RA5 PIN BLOCK DIAGRAM
MCLRE
Data Bus
RD TRISA
RD LATA
Schmitt
Trigger
Latch
QD
EN
MCLR/VPP/RA5
RD PORTA
High-Voltage Detect
Internal MCLR
Filter
HV
Low-Level
MCLR Detect
TABLE 10-1: PORTA FUNCTIONS
Name
Bit# Buffer
Function
RA0/AN0
bit 0
ST Input/output port pin or analog input.
RA1/AN1/LVDIN
bit 1
ST Input/output port pin, analog input or Low-Voltage Detect input.
RA2/AN2/VREF-
bit 2
ST Input/output port pin, analog input or VREF-.
RA3/AN3/VREF+
bit 3
ST Input/output port pin, analog input or VREF+.
RA4/T0CKI
bit 4
ST Input/output port pin or external clock input for Timer0.
Output is open-drain type.
MCLR/VPP/RA5
bit 5
ST Master Clear input or programming voltage input (if MCLR is enabled); input
only port pin or programming voltage input (if MCLR is disabled).
OSC2/CLKO/RA6 bit 6
ST OSC2, clock output or I/O pin.
OSC1/CLKI/RA7
bit 7
ST OSC1, clock input or I/O pin.
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 10-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
PORTA
LATA
TRISA
RA7⁽¹⁾ RA6⁽¹⁾
LATA7⁽¹⁾ LATA6⁽¹⁾
TRISA7⁽¹⁾ TRISA6⁽¹⁾
RA5⁽²⁾
—
—
RA4 RA3 RA2 RA1
LATA Data Output Register
PORTA Data Direction Register
RA0 xx0x 0000 uu0u 0000
xx-x xxxx uu-u uuuu
11-1 1111 11-1 1111
ADCON1 —
PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 -000 0000 -000 0000
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
Note 1: RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator
configuration; otherwise, they are read as ‘0’.
2: RA5 is an input only if MCLR is disabled.
© 2007 Microchip Technology Inc.
DS39605F-page 89