PIC18F1220_07 Datasheet, PDF (229/308 Pages) Microchip Technology – 18/20/28-Pin High-Performance, Enhanced Flash Microcontrollers with 10-bit A/D and nanoWatt Technology

PIC18F1220/1320
SUBLW
Subtract W from literal
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
[ label ] SUBLW k
0 ≤ k ≤ 255
k – (W) → W
N, OV, C, DC, Z
0000 1000 kkkk kkkk
W is subtracted from the eight-bit
literal ‘k’. The result is placed
in W.
1
1
Q2
Read
literal ‘k’
Q3
Process
Data
Q4
Write to W
Example 1:
SUBLW 0x02
Before Instruction
W
=1
C
=?
After Instruction
W
=1
C
=1
Z
=0
N
=0
; result is positive
Example 2:
SUBLW 0x02
Before Instruction
W
=2
C
=?
After Instruction
W
=0
C
=1
Z
=1
N
=0
; result is zero
Example 3:
SUBLW 0x02
Before Instruction
W
=3
C
=?
After Instruction
W
= FF
C
=0
Z
=0
N
=1
; (2’s complement)
; result is negative
SUBWF
Subtract W from f
Syntax:
[ label ] SUBWF f [,d [,a]]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – (W) → dest
Status Affected: N, OV, C, DC, Z
Encoding:
0101 11da ffff ffff
Description:
Subtract W from register ‘f’ (2’s
complement method). If ‘d’ is ‘0’,
the result is stored in W. If ‘d’ is
‘1’, the result is stored back in
register ‘f’ (default). If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ is
‘1’, then the bank will be selected
as per the BSR value (default).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example 1:
SUBWF REG
Before Instruction
REG
W
C
=3
=2
=?
After Instruction
REG
W
C
Z
N
=1
=2
=1
=0
=0
; result is positive
Example 2:
SUBWF REG, W
Before Instruction
REG
W
C
=2
=2
=?
After Instruction
REG
W
C
Z
N
=2
=0
=1
=1
=0
; result is zero
Example 3:
SUBWF REG
Before Instruction
REG
W
C
= 0x01
= 0x02
=?
After Instruction
REG
W
C
Z
N
= 0xFFh ;(2’s complement)
= 0x02
= 0x00 ;result is negative
= 0x00
= 0x01
© 2007 Microchip Technology Inc.
DS39605F-page 227