PIC18F1220_07 Datasheet, PDF (106/308 Pages) Microchip Technology – 18/20/28-Pin High-Performance, Enhanced Flash Microcontrollers with 10-bit A/D and nanoWatt Technology

PIC18F1220/1320
12.1 Timer1 Operation
Timer1 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
When TMR1CS = 0, Timer1 increments every instruc-
tion cycle. When TMR1CS = 1, Timer1 increments on
every rising edge of the external clock input, or the
Timer1 oscillator, if enabled.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RB7/PGD/T1OSI/P1D/KBI3 and RB6/T1OSO/
T13CKI/P1C/KBI2 pins become inputs. That is, the
TRISB7:TRISB6 values are ignored and the pins read
as ‘0’.
Timer1 also has an internal “Reset input”. This Reset
can be generated by the CCP module (see
Section 15.4.4 “Special Event Trigger”).
FIGURE 12-1:
TIMER1 BLOCK DIAGRAM
TMR1IF
Overflow
Interrupt
Flag bit
T13CKI/T1OSO
T1OSI
CCP Special Event Trigger
TMR1
CLR
TMR1H TMR1L
T1OSC
T1OSCEN
Enable
Oscillator⁽¹⁾
Synchronized
0
Clock Input
TMR1ON
On/Off
1
T1SYNC
FOSC/4
Internal
Clock
1
Prescaler
1, 2, 4, 8
0
2
T1CKPS1:T1CKPS0
TMR1CS
Synchronize
det
Peripheral Clocks
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off. This eliminates
power drain.
FIGURE 12-2:
TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE
Data Bus<7:0>
8
TMR1H
8
8
Write TMR1L
Read TMR1L
CCP Special Event Trigger
TMR1IF
Overflow
Interrupt
Flag bit
T13CKI/T1OSO
T1OSI
8
TMR1
Timer 1
High Byte
CLR
TMR1L
T1OSC
T1OSCEN
Enable
Oscillator⁽¹⁾
Synchronized
0
Clock Input
TMR1ON
on/off
1
T1SYNC
1
FOSC/4
Internal
Clock
0
TMR1CS
Prescaler
1, 2, 4, 8
2
T1CKPS1:T1CKPS0
Synchronize
det
Peripheral Clocks
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
DS39605F-page 104
© 2007 Microchip Technology Inc.