PIC18F1220_07 Datasheet, PDF (185/308 Pages) Microchip Technology – 18/20/28-Pin High-Performance, Enhanced Flash Microcontrollers with 10-bit A/D and nanoWatt Technology

PIC18F1220/1320
19.4.2 EXITING FAIL-SAFE OPERATION
The Fail-Safe condition is terminated by either a device
Reset, or by entering a power managed mode. On
Reset, the controller starts the primary clock source
specified in Configuration Register 1H (with any
required start-up delays that are required for the
oscillator mode, such as OST or PLL timer). The
INTOSC multiplexer provides the system clock until the
primary clock source becomes ready (similar to a Two-
Speed Start-up). The clock system source is then
switched to the primary clock (indicated by the OSTS
bit in the OSCCON register becoming set). The Fail-
Safe Clock Monitor then resumes monitoring the
peripheral clock.
The primary clock source may never become ready
during start-up. In this case, operation is clocked by the
INTOSC multiplexer. The OSCCON register will remain
in its Reset state until a power managed mode is
entered.
Entering a power managed mode by loading the
OSCCON register and executing a SLEEP instruction
will clear the Fail-Safe condition. When the Fail-Safe
condition is cleared, the clock monitor will resume
monitoring the peripheral clock.
19.4.3 FSCM INTERRUPTS IN POWER
MANAGED MODES
As previously mentioned, entering a power managed
mode clears the Fail-Safe condition. By entering a
power managed mode, the clock multiplexer selects
the clock source selected by the OSCCON register.
Fail-Safe monitoring of the power managed clock
source resumes in the power managed mode.
If an oscillator failure occurs during power managed
operation, the subsequent events depend on whether
or not the oscillator failure interrupt is enabled. If
enabled (OSCFIF = 1), code execution will be clocked
by the INTOSC multiplexer. An automatic transition
back to the failed clock source will not occur.
If the interrupt is disabled, the device will not exit the
power managed mode on oscillator failure. Instead, the
device will continue to operate as before, but clocked
by the INTOSC multiplexer. While in Idle mode, subse-
quent interrupts will cause the CPU to begin executing
instructions while being clocked by the INTOSC multi-
plexer. The device will not transition to a different clock
source until the Fail-Safe condition is cleared.
FIGURE 19-4:
FSCM TIMING DIAGRAM
Sample Clock
System
Clock
Output
CM Output
(Q)
OSCFIF
Oscillator
Failure
Failure
Detected
Note:
CM Test
CM Test
CM Test
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
© 2007 Microchip Technology Inc.
DS39605F-page 183