PIC18F1220_07 Datasheet, PDF (117/308 Pages) Microchip Technology – 18/20/28-Pin High-Performance, Enhanced Flash Microcontrollers with 10-bit A/D and nanoWatt Technology

PIC18F1220/1320
15.0 ENHANCED CAPTURE/
COMPARE/PWM (ECCP)
MODULE
The Enhanced CCP module is implemented as a
standard CCP module with Enhanced PWM
capabilities. These capabilities allow for 2 or 4 output
channels, user-selectable polarity, dead-band control
and automatic shutdown and restart and are discussed
in detail in Section 15.5 “Enhanced PWM Mode”.
The control register for CCP1 is shown in Register 15-1.
In addition to the expanded functions of the CCP1CON
register, the ECCP module has two additional
registers associated with Enhanced PWM operation
and auto-shutdown features:
• PWM1CON
• ECCPAS
REGISTER 15-1:
CCP1CON REGISTER FOR ENHANCED CCP OPERATION
R/W-0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
P1M1
P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2
bit 7
R/W-0
CCP1M1
R/W-0
CCP1M0
bit 0
bit 7-6
bit 5-4
bit 3-0
P1M1:P1M0: PWM Output Configuration bits
If CCP1M<3:2> = 00, 01, 10:
xx = P1A assigned as Capture/Compare input; P1B, P1C, P1D assigned as port pins
If CCP1M<3:2> = 11:
00 = Single output; P1A modulated; P1B, P1C, P1D assigned as port pins
01 = Full-bridge output forward; P1D modulated; P1A active; P1B, P1C inactive
10 = Half-bridge output; P1A, P1B modulated with dead-band control; P1C, P1D assigned as
port pins
11 = Full-bridge output reverse; P1B modulated; P1C active; P1A, P1D inactive
DC1B1:DC1B0: PWM Duty Cycle Least Significant bits
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L.
CCP1M3:CCP1M0: ECCP1 Mode Select bits
0000 = Capture/Compare/PWM off (resets ECCP module)
0001 = Unused (reserved)
0010 = Compare mode, toggle output on match (ECCP1IF bit is set)
0011 = Unused (reserved)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (ECCP1IF bit is set)
1001 = Compare mode, clear output on match (ECCP1IF bit is set)
1010 = Compare mode, generate software interrupt on match (ECCP1IF bit is set,
ECCP1 pin returns to port pin operation)
1011 = Compare mode, trigger special event (ECCP1IF bit is set; ECCP resets TMR1 or
TMR3 and starts an A/D conversion if the A/D module is enabled)
1100 = PWM mode; P1A, P1C active-high; P1B, P1D active-high
1101 = PWM mode; P1A, P1C active-high; P1B, P1D active-low
1110 = PWM mode; P1A, P1C active-low; P1B, P1D active-high
1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc.
DS39605F-page 115