PIC18F1220_07 Datasheet, PDF(166/308 Page) Microchip Technology – 18/20/28-Pin High-Performance, Enhanced Flash Microcontrollers with 10-bit A/D and nanoWatt Technology

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PIC18F1220_07 Datasheet, PDF (166/308 Pages) Microchip Technology – 18/20/28-Pin High-Performance, Enhanced Flash Microcontrollers with 10-bit A/D and nanoWatt Technology

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PIC18F1220/1320

17.8 Use of the CCP1 Trigger

An A/D conversion can be started by the âspecial event

triggerâ of the CCP1 module. This requires that the

CCP1M3:CCP1M0 bits (CCP1CON<3:0>) be pro-

grammed as â1011â and that the A/D module is enabled

(ADON bit is set). When the trigger occurs, the

GO/DONE bit will be set, starting the A/D acquisition

and conversion and the Timer1 (or Timer3) counter will

be reset to zero. Timer1 (or Timer3) is reset to auto-

matically repeat the A/D acquisition period with minimal

software overhead (moving ADRESH/ADRESL to the

desired location). The appropriate analog input

channel must be selected and the minimum acquisition

period is either timed by the user, or an appropriate

TACQ time selected before the âspecial event triggerâ

sets the GO/DONE bit (starts a conversion).

If the A/D module is not enabled (ADON is cleared), the

âspecial event triggerâ will be ignored by the A/D

module, but will still reset the Timer1 (or Timer3)

counter.

TABLE 17-2: SUMMARY OF A/D REGISTERS

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3 Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

all other

Resets

INTCON

GIE/

GIEH

PEIE/ TMR0IE INT0IE

GIEL

RBIE TMR0IF INT0IF

RBIF 0000 0000 0000 0000

PIR1

â

ADIF

RCIF

TXIF

â CCP1IF TMR2IF TMR1IF -000 -000 -000 -000

PIE1

â

ADIE

RCIE

TXIE

â CCP1IE TMR2IE TMR1IE -000 -000 -000 -000

IPR1

â

ADIP

RCIP

TXIP

â CCP1IP TMR2IP TMR1IP -111 -111 -111 -111

PIR2

OSCFIF

â

â

EEIF

â

LVDIF TMR3IF

â 0--0 -00- 0--0 -00-

PIE2

OSCFIE

â

â

EEIE

â

LVDIE TMR3IE

â 0--0 -00- 0--0 -00-

IPR2

OSCFIP

â

â

EEIP

â

LVDIP TMR3IP

â 1--1 -11- 1--1 -11-

ADRESH A/D Result Register High Byte

xxxx xxxx uuuu uuuu

ADRESL A/D Result Register Low Byte

xxxx xxxx uuuu uuuu

ADCON0 VCFG1 VCFG0

â

CHS2 CHS1 CHS0 GO/DONE ADON 00-0 0000 00-0 0000

ADCON1

â

PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 -000 0000 -000 0000

ADCON2

PORTA

TRISA

ADFM

RA7(3)

TRISA7(3)

â

RA6(2)

TRISA6(2)

ACQT2

RA5(1)

â

ACQT1 ACQT0 ADCS2

RA4

RA3

RA2

PORTA Data Direction Register

ADCS1

RA1

ADCS0

RA0

0-00 0000 0-00 0000

qq0x 0000 uu0u 0000

qq-1 1111 11-1 1111

PORTB Read PORTB pins, Write LATB Latch

xxxx xxxx uuuu uuuu

TRISB PORTB Data Direction Register

1111 1111 1111 1111

LATB

PORTB Output Data Latch

xxxx xxxx uuuu uuuu

Legend:

Note 1:

2:

3:

x = unknown, u = unchanged, q = depends on CONFIG1H<3:0>, â = unimplemented, read as â0â.

Shaded cells are not used for A/D conversion.

RA5 port bit is available only as an input pin when the MCLRE bit in the configuration register is â0â.

RA6 and TRISA6 are available only when the primary oscillator mode selection offers RA6 as a port pin; otherwise, RA6

always reads â0â, TRISA6 always reads â1â and writes to both are ignored (see CONFIG1H<3:0>).

RA7 and TRISA7 are available only when the internal RC oscillator is configured as the primary oscillator in

CONFIG1H<3:0>; otherwise, RA7 always reads â0â, TRISA7 always reads â1â and writes to both are ignored.

DS39605F-page 164

Â© 2007 Microchip Technology Inc.

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