PIC18F1220_07 Datasheet, PDF (72/308 Pages) Microchip Technology – 18/20/28-Pin High-Performance, Enhanced Flash Microcontrollers with 10-bit A/D and nanoWatt Technology

PIC18F1220/1320
7.7 Operation During Code-Protect
Data EEPROM memory has its own code-protect bits in
configuration words. External read and write
operations are disabled if either of these mechanisms
are enabled.
The microcontroller itself can both read and write to the
internal data EEPROM, regardless of the state of the
code-protect configuration bit. Refer to Section 19.0
“Special Features of the CPU” for additional
information.
7.8 Using the Data EEPROM
The data EEPROM is a high endurance, byte address-
able array that has been optimized for the storage of fre-
quently changing information (e.g., program variables or
other data that are updated often). Frequently changing
values will typically be updated more often than specifi-
cation D124. If this is not the case, an array refresh must
be performed. For this reason, variables that change
infrequently (such as constants, IDs, calibration, etc.)
should be stored in Flash program memory.
A simple data EEPROM refresh routine is shown in
Example 7-3.
Note:
If data EEPROM is only used to store
constants and/or data that changes rarely,
an array refresh is likely not required. See
specification D124.
EXAMPLE 7-3:
Loop
CLRF
BCF
BCF
BCF
BSF
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BTFSC
BRA
INCFSZ
BRA
DATA EEPROM REFRESH ROUTINE
EEADR
EECON1, CFGS
EECON1, EEPGD
INTCON, GIE
EECON1, WREN
EECON1, RD
55h
EECON2
AAh
EECON2
EECON1, WR
EECON1, WR
$-2
EEADR, F
Loop
; Start at address 0
; Set for memory
; Set for Data EEPROM
; Disable interrupts
; Enable writes
; Loop to refresh array
; Read current address
;
; Write 55h
;
; Write AAh
; Set WR bit to begin write
; Wait for write to complete
; Increment address
; Not zero, do it again
BCF
EECON1, WREN
BSF
INTCON, GIE
; Disable writes
; Enable interrupts
TABLE 7-1: REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
Resets
INTCON GIE/GIEH PEIE/GIEL TMR0IE INTE
RBIE TMR0IF INTF
RBIF 0000 000x 0000 000u
EEADR EEPROM Address Register
0000 0000 0000 0000
EEDATA EEPROM Data Register
0000 0000 0000 0000
EECON2 EEPROM Control Register 2 (not a physical register)
—
—
EECON1 EEPGD
CFGS
—
FREE WRERR WREN WR
RD xx-0 x000 uu-0 u000
IPR2
OSCFIP
—
—
EEIP
—
LVDIP TMR3IP — 1--1 -11- 1--1 -11-
PIR2
OSCFIF
—
—
EEIF
—
LVDIF TMR3IF
— 0--0 -00- 0--0 -00-
PIE2
OSCFIE
—
—
EEIE
—
LVDIE TMR3IE — 0--0 -00- 0--0 -00-
Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.
DS39605F-page 70
© 2007 Microchip Technology Inc.