PIC18F1220_07 Datasheet, PDF (64/308 Pages) Microchip Technology – 18/20/28-Pin High-Performance, Enhanced Flash Microcontrollers with 10-bit A/D and nanoWatt Technology

PIC18F1220/1320
6.4 Erasing Flash Program Memory
The minimum erase block size is 32 words or 64 bytes
under firmware control. Only through the use of an
external programmer, or through ICSP control, can
larger blocks of program memory be bulk erased. Word
erase in Flash memory is not supported.
When initiating an erase sequence from the micro-
controller itself, a block of 64 bytes of program memory
is erased. The Most Significant 16 bits of the
TBLPTR<21:6> point to the block being erased.
TBLPTR<5:0> are ignored.
The EECON1 register commands the erase operation.
The EEPGD bit must be set to point to the Flash
program memory. The CFGS bit must be clear to
access program Flash and data EEPROM memory.
The WREN bit must be set to enable write operations.
The FREE bit is set to select an erase operation. The
WR bit is set as part of the required instruction
sequence (as shown in Example 6-2) and starts the
actual erase operation. It is not necessary to load the
TABLAT register with any data as it is ignored.
For protection, the write initiate sequence using
EECON2 must be used.
A long write is necessary for erasing the internal Flash.
Instruction execution is halted while in a long write
cycle. The long write will be terminated by the internal
programming timer.
6.4.1
FLASH PROGRAM MEMORY
ERASE SEQUENCE
The sequence of events for erasing a block of internal
program memory location is:
1. Load Table Pointer with address of row being
erased.
2. Set the EECON1 register for the erase operation:
• set EEPGD bit to point to program memory;
• clear the CFGS bit to access program
memory;
• set WREN bit to enable writes;
• set FREE bit to enable the erase.
3. Disable interrupts.
4. Write 55h to EECON2.
5. Write AAh to EECON2.
6. Set the WR bit. This will begin the row erase
cycle.
7. The CPU will stall for duration of the erase
(about 2 ms using internal timer).
8. Execute a NOP.
9. Re-enable interrupts.
EXAMPLE 6-2: ERASING A FLASH PROGRAM MEMORY ROW
ERASE_ROW
Required
Sequence
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
BSF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
EECON1, EEPGD
EECON1, WREN
EECON1, FREE
INTCON, GIE
55h
EECON2
AAh
EECON2
EECON1, WR
INTCON, GIE
; load TBLPTR with the base
; address of the memory block
; point to FLASH program memory
; enable write to memory
; enable Row Erase operation
; disable interrupts
; write 55H
; write AAH
; start erase (CPU stall)
; re-enable interrupts
DS39605F-page 62
© 2007 Microchip Technology Inc.