PIC18F1220_07 Datasheet, PDF (149/308 Pages) Microchip Technology – 18/20/28-Pin High-Performance, Enhanced Flash Microcontrollers with 10-bit A/D and nanoWatt Technology

PIC18F1220/1320
16.3.6.2 Receiving a Break Sync
To receive a Break Sync:
1. Configure the EUSART for asynchronous
transmit and receive. TXEN should remain
clear. SPBRGH:SPBRG may be left as is.
2. Enable auto-wake-up. Set WUE.
3. Enable RXIF interrupts. Set RCIE, PEIE, GIE.
4. The controller may be placed in any power
managed mode.
5. An RCIF will be generated at the beginning of
the Break signal. When the interrupt is received,
read RCREG to clear RCIF and discard. Allow
the controller to return to PRI_RUN mode.
6. Wait for the RX line to go high at the end of the
Break signal. Wait for any of the following: WUE
to clear automatically (poll), RB4/RX to go high
(poll) or for RBIF to be set (poll or interrupt). If
RBIF is used, check to be sure that RB4/RX is
high before continuing.
7. Enable Auto-Baud Rate Detect. Set ABDEN.
8. Return from the interrupt. Allow the primary
clock to start and stabilize (PRI_RUN or
PRI_IDLE).
9. When the next RCIF interrupt occurs, the
received baud rate has been measured. Read
RCREG to clear RCIF and discard. Check
SPBRGH:SPBRG for a valid value. The
EUSART is ready for normal communications.
Return from the interrupt. Allow the primary
clock to run (PRI_RUN or PRI_IDLE).
10. Process subsequent RCIF interrupts normally
as in asynchronous reception. TXEN should
now be set if transmissions are needed. TXIF
and TXIE may be set if transmit interrupts are
desired. Remain in PRI_RUN or PRI_IDLE until
communications are complete. Clear TXEN and
return to step 2.
FIGURE 16-9:
SEND BREAK CHARACTER SEQUENCE
Write to TXREG
BRG Output
(Shift Clock)
TX (pin)
Dummy Write
Start Bit
Bit 0
Bit 1
Break
Bit 11
Stop Bit
TXIF bit
TRMT bit
SENDB
© 2007 Microchip Technology Inc.
DS39605F-page 147