PIC18F1220_07 Datasheet, PDF (73/308 Pages) Microchip Technology – 18/20/28-Pin High-Performance, Enhanced Flash Microcontrollers with 10-bit A/D and nanoWatt Technology

PIC18F1220/1320
8.0 8 x 8 HARDWARE MULTIPLIER
8.1 Introduction
An 8 x 8 hardware multiplier is included in the ALU of
the PIC18F1220/1320 devices. By making the multiply
a hardware operation, it completes in a single instruc-
tion cycle. This is an unsigned multiply that gives a
16-bit result. The result is stored into the 16-bit product
register pair (PRODH:PRODL). The multiplier does not
affect any flags in the Status register.
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
• Higher computational throughput
• Reduces code size requirements for multiply
algorithms
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
Table 8-1 shows a performance comparison between
Enhanced devices using the single-cycle hardware
multiply and performing the same function without the
hardware multiply.
TABLE 8-1: PERFORMANCE COMPARISON
Routine
Multiply Method
Program
Memory
(Words)
Without hardware multiply
13
8 x 8 unsigned
Hardware multiply
1
8 x 8 signed
Without hardware multiply
33
Hardware multiply
6
Without hardware multiply
21
16 x 16 unsigned
Hardware multiply
28
Without hardware multiply
52
16 x 16 signed
Hardware multiply
35
Cycles
(Max)
69
1
91
6
242
28
254
40
Time
@ 40 MHz @ 10 MHz @ 4 MHz
6.9 μs
100 ns
9.1 μs
600 ns
24.2 μs
2.8 μs
25.4 μs
4 μs
27.6 μs
400 ns
36.4 μs
2.4 μs
96.8 μs
11.2 μs
102.6 μs
16 μs
69 μs
1 μs
91 μs
6 μs
242 μs
28 μs
254 μs
40 μs
8.2 Operation
Example 8-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
Example 8-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument’s Most Significant bit (MSb) is tested
and the appropriate subtractions are done.
EXAMPLE 8-1:
MOVF ARG1, W
MULWF ARG2
8 x 8 UNSIGNED
MULTIPLY ROUTINE
;
; ARG1 * ARG2 ->
; PRODH:PRODL
EXAMPLE 8-2:
MOVF ARG1, W
MULWF ARG2
BTFSC ARG2, SB
SUBWF PRODH, F
MOVF
BTFSC
SUBWF
ARG2, W
ARG1, SB
PRODH, F
8 x 8 SIGNED MULTIPLY
ROUTINE
; ARG1 * ARG2 ->
; PRODH:PRODL
; Test Sign Bit
; PRODH = PRODH
;
- ARG1
; Test Sign Bit
; PRODH = PRODH
;
- ARG2
© 2007 Microchip Technology Inc.
DS39605F-page 71