PIC18F1220_07 Datasheet, PDF (40/308 Pages) Microchip Technology – 18/20/28-Pin High-Performance, Enhanced Flash Microcontrollers with 10-bit A/D and nanoWatt Technology

PIC18F1220/1320
TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable
Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
TMR3H
1220 1320
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR3L
1220 1320
xxxx xxxx
uuuu uuuu
uuuu uuuu
T3CON
1220 1320
0-00 0000
u-uu uuuu
u-uu uuuu
SPBRGH
1220 1320
0000 0000
0000 0000
uuuu uuuu
SPBRG
1220 1320
0000 0000
0000 0000
uuuu uuuu
RCREG
1220 1320
0000 0000
0000 0000
uuuu uuuu
TXREG
1220 1320
0000 0000
0000 0000
uuuu uuuu
TXSTA
1220 1320
0000 0010
0000 0010
uuuu uuuu
RCSTA
1220 1320
0000 000x
0000 000x
uuuu uuuu
BAUDCTL
1220 1320
-1-1 0-00
-1-1 0-00
-u-u u-uu
EEADR
1220 1320
0000 0000
0000 0000
uuuu uuuu
EEDATA
1220 1320
0000 0000
0000 0000
uuuu uuuu
EECON2
1220 1320
0000 0000
0000 0000
0000 0000
EECON1
1220 1320
xx-0 x000
uu-0 u000
uu-0 u000
IPR2
PIR2
1220 1320
1220 1320
1--1 -11-
0--0 -00-
1--1 -11-
0--0 -00-
u--u -uu-
u--u -uu-⁽¹⁾
PIE2
1220 1320
0--0 -00-
0--0 -00-
u--u -uu-
IPR1
PIR1
1220 1320
1220 1320
-111 -111
-000 -000
-111 -111
-000 -000
-uuu -uuu
-uuu -uuu⁽¹⁾
PIE1
1220 1320
-000 -000
-000 -000
-uuu -uuu
OSCTUNE
1220 1320
--00 0000
--00 0000
--uu uuuu
TRISB
TRISA⁽⁵⁾
1220 1320
1220 1320
1111 1111
11-1 1111⁽⁵⁾
1111 1111
11-1 1111⁽⁵⁾
uuuu uuuu
uu-u uuuu⁽⁵⁾
LATB
LATA⁽⁵⁾
1220 1320
1220 1320
xxxx xxxx
xx-x xxxx⁽⁵⁾
uuuu uuuu
uu-u uuuu⁽⁵⁾
uuuu uuuu
uu-u uuuu⁽⁵⁾
PORTB
PORTA^(5,6)
1220 1320
1220 1320
xxxx xxxx
xx0x 0000^(5,6)
uuuu uuuu
uu0u 0000^(5,6)
uuuu uuuu
uuuu uuuu^(5,6)
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-2 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the Oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
6: Bit 5 of PORTA is enabled if MCLR is disabled.
DS39605F-page 38
© 2007 Microchip Technology Inc.