PIC18F1220_07 Datasheet, PDF (114/308 Pages) Microchip Technology – 18/20/28-Pin High-Performance, Enhanced Flash Microcontrollers with 10-bit A/D and nanoWatt Technology

PIC18F1220/1320
14.1 Timer3 Operation
Timer3 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
The operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>).
When TMR3CS = 0, Timer3 increments every instruc-
tion cycle. When TMR3CS = 1, Timer3 increments on
every rising edge of the Timer1 external clock input or
the Timer1 oscillator, if enabled.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RB7/PGD/T1OSI/P1D/KBI3 and RB6/PGC/
T1OSO/T13CKI/P1C/KBI2 pins become inputs. That
is, the TRISB7:TRISB6 value is ignored and the pins
are read as ‘0’.
Timer3 also has an internal “Reset input”. This Reset
can be generated by the CCP module (see
Section 15.4.4 “Special Event Trigger”).
FIGURE 14-1:
TIMER3 BLOCK DIAGRAM
TMR3IF
Overflow
Interrupt
Flag bit
TMR3H
CLR
TMR3L
CCP Special Event Trigger
T3CCPx
Synchronized
0
Clock Input
TMR3ON
On/Off
1
T3SYNC
T1OSO/
T13CKI
T1OSI
T1OSC
1
T1OSCEN _FOSC/4
Enable
Oscillator⁽¹⁾
Internal
Clock
0
TMR3CS
Prescaler
1, 2, 4, 8
2
Synchronize
det
Peripheral Clocks
T3CKPS1:T3CKPS0
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
FIGURE 14-2:
TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE
Data Bus<7:0>
8
TMR3H
8
8
Write TMR3L
Read TMR3L
Set TMR3IF Flag bit
on Overflow
8
TMR3
Timer3
High Byte
CLR
TMR3L
T1OSO/
T13CKI
T1OSI
To Timer1 Clock Input
T1OSC
T1OSCEN
Enable
Oscillator⁽¹⁾
CCP Special Event Trigger
T3CCPx
0
Synchronized
Clock Input
TMR3ON
On/Off
1
T3SYNC
FOSC/4
Internal
Clock
1
Prescaler
1, 2, 4, 8
0
2
T3CKPS1:T3CKPS0
TMR3CS
Synchronize
det
Peripheral
Clocks
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
DS39605F-page 112
© 2007 Microchip Technology Inc.