PIC18F1220_07 Datasheet, PDF (302/308 Pages) Microchip Technology – 18/20/28-Pin High-Performance, Enhanced Flash Microcontrollers with 10-bit A/D and nanoWatt Technology

PIC18F1220/1320
OSCTUNE (Oscillator Tuning) ................................... 15
PIE1 (Peripheral Interrupt Enable 1) .......................... 80
PIE2 (Peripheral Interrupt Enable 2) .......................... 81
PIR1 (Peripheral Interrupt Request (Flag) 1) ............. 78
PIR2 (Peripheral Interrupt Request (Flag) 2) ............. 79
PWM1CON (PWM Configuration) ............................ 126
RCON (Reset Control) ......................................... 56, 84
RCSTA (Receive Status and Control) ...................... 133
Status ......................................................................... 55
STKPTR (Stack Pointer) ............................................ 43
T0CON (Timer0 Control) ............................................ 99
T1CON (Timer 1 Control) ......................................... 103
T2CON (Timer 2 Control) ......................................... 109
T3CON (Timer3 Control) .......................................... 111
TXSTA (Transmit Status and Control) ..................... 132
WDTCON (Watchdog Timer Control) ....................... 180
RESET ............................................................................. 221
Reset .......................................................................... 33, 171
RETFIE ............................................................................ 222
RETLW ............................................................................. 222
RETURN .......................................................................... 223
Return Address Stack ........................................................ 42
and Associated Registers .......................................... 42
Return Stack Pointer (STKPTR) ........................................ 42
Revision History ............................................................... 291
RLCF ................................................................................ 223
RLNCF ............................................................................. 224
RRCF ............................................................................... 224
RRNCF ............................................................................. 225
S
SETF ................................................................................ 225
SLEEP .............................................................................. 226
Sleep
OSC1 and OSC2 Pin States ...................................... 18
Software Simulator (MPLAB SIM) .................................... 234
Special Event Trigger. See Compare
Special Features of the CPU ............................................ 171
Configuration Registers .................................... 172–178
Special Function Registers ................................................ 49
Map ............................................................................ 49
Stack Full/Underflow Resets .............................................. 43
SUBFWB .......................................................................... 226
SUBLW ............................................................................ 227
SUBWF ............................................................................ 227
SUBWFB .......................................................................... 228
SWAPF ............................................................................ 228
T
TABLAT Register ............................................................... 60
Table Pointer Operations (table) ........................................ 60
TBLPTR Register ............................................................... 60
TBLRD ............................................................................. 229
TBLWT ............................................................................. 230
Time-out Sequence ............................................................ 34
Timer0 ................................................................................ 99
16-Bit Mode Timer Reads and Writes ...................... 101
Associated Registers ............................................... 101
Clock Source Edge Select (T0SE Bit) ...................... 101
Clock Source Select (T0CS Bit) ............................... 101
Operation ................................................................. 101
Overflow Interrupt ..................................................... 101
Prescaler. See Prescaler, Timer0.
Switching Prescaler Assignment .............................. 101
Timer1 .............................................................................. 103
16-Bit Read/Write Mode .......................................... 106
Associated Registers ............................................... 108
Interrupt ................................................................... 106
Operation ................................................................. 104
Oscillator ...........................................................103, 105
Layout Considerations ..................................... 106
Overflow Interrupt .................................................... 103
Resetting, Using a Special Event Trigger
Output (CCP) ................................................... 106
Special Event Trigger (CCP) ................................... 117
TMR1H Register ...................................................... 103
TMR1L Register ....................................................... 103
Use as a Real-Time Clock ....................................... 107
Timer2 .............................................................................. 109
Associated Registers ............................................... 110
Operation ................................................................. 109
Output ...................................................................... 110
Postscaler. See Postscaler, Timer2.
PR2 Register ....................................................109, 119
Prescaler. See Prescaler, Timer2.
TMR2 Register ......................................................... 109
TMR2 to PR2 Match Interrupt ...................109, 110, 119
Timer3 .............................................................................. 111
Associated Registers ............................................... 113
Operation ................................................................. 112
Oscillator ...........................................................111, 113
Overflow Interrupt .............................................111, 113
Special Event Trigger (CCP) ................................... 113
TMR3H Register ...................................................... 111
TMR3L Register ....................................................... 111
Timing Diagrams
A/D Conversion ........................................................ 265
Asynchronous Reception ......................................... 144
Asynchronous Transmission .................................... 141
Asynchronous Transmission (Back to Back) ........... 142
Auto-Wake-up Bit (WUE) During
Normal Operation ............................................ 145
Auto-Wake-up Bit (WUE) During Sleep ................... 145
Brown-out Reset (BOR) ........................................... 260
Capture/Compare/PWM (All CCP Modules) ............ 262
CLKO and I/O .......................................................... 259
Clock/Instruction Cycle .............................................. 45
EUSART Synchronous Receive
(Master/Slave) ................................................. 264
EUSART SynchronousTransmission
(Master/Slave) ................................................. 263
External Clock (All Modes Except PLL) ................... 257
Fail-Safe Clock Monitor ........................................... 183
Low-Voltage Detect ................................................. 168
Low-Voltage Detect Characteristics ......................... 253
PWM Auto-Shutdown (PRSEN = 0,
Auto-Restart Disabled) .................................... 128
PWM Auto-Shutdown (PRSEN = 1,
Auto-Restart Enabled) ..................................... 128
Reset, Watchdog Timer (WDT), Oscillator Start-up
Timer (OST) and Power-up Timer (PWRT) ..... 260
Send Break Character Sequence ............................ 147
Slow Rise Time (MCLR Tied to VDD,
VDD Rise > TPWRT) ............................................ 40
Synchronous Reception
(Master Mode, SREN) ..................................... 150
Synchronous Transmission ..................................... 148
Synchronous Transmission (Through TXEN) .......... 149
DS39605F-page 300
© 2007 Microchip Technology Inc.