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PIC18F1220_07 Datasheet, PDF (226/308 Pages) Microchip Technology – 18/20/28-Pin High-Performance, Enhanced Flash Microcontrollers with 10-bit A/D and nanoWatt Technology | |||
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PIC18F1220/1320
RLNCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Rotate Left f (no carry)
[ label ] RLNCF f [,d [,a]]
0 ⤠f ⤠255
d â [0,1]
a â [0,1]
(f<n>) â dest<n + 1>,
(f<7>) â dest<0>
N, Z
0100 01da ffff ffff
The contents of register âfâ are
rotated one bit to the left. If âdâ is â0â,
the result is placed in W. If âdâ is â1â,
the result is stored back in register
âfâ (default). If âaâ is â0â, the Access
Bank will be selected, overriding
the BSR value. If âaâ is â1â, then the
bank will be selected as per the
BSR value (default).
register f
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Decode
Read
register âfâ
Q3
Process
Data
Q4
Write to
destination
Example:
RLNCF REG
Before Instruction
REG = 1010 1011
After Instruction
REG = 0101 0111
RRCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Rotate Right f through Carry
[ label ] RRCF f [,d [,a]]
0 ⤠f ⤠255
d â [0,1]
a â [0,1]
(f<n>) â dest<n â 1>,
(f<0>) â C,
(C) â dest<7>
C, N, Z
0011 00da ffff ffff
The contents of register âfâ are
rotated one bit to the right through
the Carry flag. If âdâ is â0â, the result
is placed in W. If âdâ is â1â, the result
is placed back in register âfâ
(default). If âaâ is â0â, the Access
Bank will be selected, overriding
the BSR value. If âaâ is â1â, then the
bank will be selected as per the
BSR value (default).
C
register f
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Decode
Read
register âfâ
Q3
Process
Data
Q4
Write to
destination
Example:
RRCF REG, W
Before Instruction
REG
C
= 1110 0110
=0
After Instruction
REG
W
C
= 1110 0110
= 0111 0011
=0
DS39605F-page 224
© 2007 Microchip Technology Inc.
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