PIC18F1220_07 Datasheet, PDF (52/308 Pages) Microchip Technology – 18/20/28-Pin High-Performance, Enhanced Flash Microcontrollers with 10-bit A/D and nanoWatt Technology

PIC18F1220/1320
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F1220/1320)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details on
POR, BOR page:
TOSU
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000 36, 42
TOSH
Top-of-Stack High Byte (TOS<15:8>)
0000 0000 36, 42
TOSL
Top-of-Stack Low Byte (TOS<7:0>)
0000 0000 36, 42
STKPTR
PCLATU
STKFUL
—
STKUNF
—
—
Return Stack Pointer
bit 21⁽³⁾ Holding Register for PC<20:16>
00-0 0000
---0 0000
36, 43
36, 44
PCLATH
Holding Register for PC<15:8>
0000 0000 36, 44
PCL
PC Low Byte (PC<7:0>)
0000 0000 36, 44
TBLPTRU
—
—
bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
--00 0000 36, 60
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
0000 0000 36, 60
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
0000 0000 36, 60
TABLAT
Program Memory Table Latch
0000 0000 36, 60
PRODH
Product Register High Byte
xxxx xxxx 36, 71
PRODL
Product Register Low Byte
xxxx xxxx 36, 71
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF 0000 000x 36, 75
INTCON2
RBPU INTEDG0 INTEDG1 INTEDG2
—
TMR0IP
—
RBIP 1111 -1-1 36, 76
INTCON3
INT2IP
INT1IP
—
INT2IE
INT1IE
—
INT2IF
INT1IF 11-0 0-00 36, 77
INDF0
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
N/A
36, 53
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
N/A
36, 53
POSTDEC0 Uses contents of FSR0 to address data memory– value of FSR0 post-decremented (not a physical register)
N/A
36, 53
PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
N/A
36, 53
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 offset by W (not a physical register)
N/A
36, 53
FSR0H
—
—
—
—
Indirect Data Memory Address Pointer 0 High
---- 0000 36, 53
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
xxxx xxxx 36, 53
WREG
Working Register
xxxx xxxx
36
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
N/A
36, 53
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
N/A
36, 53
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
N/A
36, 53
PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
N/A
36, 53
PLUSW1
Uses contents of FSR1 to address data memory – value of FSR1 offset by W (not a physical register)
N/A
36, 53
FSR1H
—
—
—
—
Indirect Data Memory Address Pointer 1 High
---- 0000 36, 53
FSR1L
Indirect Data Memory Address Pointer 1 Low Byte
xxxx xxxx 36, 53
BSR
—
—
—
—
Bank Select Register
---- 0000 37, 52
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
N/A
37, 53
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
N/A
37, 53
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
N/A
37, 53
PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
N/A
37, 53
PLUSW2
Uses contents of FSR2 to address data memory – value of FSR2 offset by W (not a physical register)
N/A
37, 53
FSR2H
—
—
—
—
Indirect Data Memory Address Pointer 2 High
---- 0000 37, 53
FSR2L
Indirect Data Memory Address Pointer 2 Low Byte
xxxx xxxx 37, 53
STATUS
—
—
—
N
OV
Z
DC
C
---x xxxx 37, 55
TMR0H
Timer0 Register High Byte
0000 0000 37, 101
TMR0L
Timer0 Register Low Byte
xxxx xxxx 37, 101
T0CON
TMR0ON T08BIT
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0 1111 1111 37, 99
OSCCON
IDLEN
IRCF2
IRCF1
IRCF0
OSTS
IOFS
SCS1
SCS0 0000 q000 37, 17
LVDCON
—
—
IVRST
LVDEN
LVDL3
LVDL2
LVDL1
LVDL0 --00 0101 37, 167
WDTCON
—
—
—
—
—
—
—
SWDTEN --- ---0 37, 180
RCON
IPEN
—
—
RI
TO
PD
POR
BOR 0--1 11q0 35, 56, 84
Legend:
Note 1:
2:
3:
4:
x = unknown, u = unchanged, – = unimplemented, q = value depends on condition
RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator mode only and read ‘0’
in all other oscillator modes.
RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read ‘0’ in all other modes.
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
The RA5 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’. Otherwise, RA5 reads ‘0’. This bit is read-only.
DS39605F-page 50
© 2007 Microchip Technology Inc.