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PIC18F1220_07 Datasheet, PDF (38/308 Pages) Microchip Technology – 18/20/28-Pin High-Performance, Enhanced Flash Microcontrollers with 10-bit A/D and nanoWatt Technology
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PIC18F1220/1320
TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register
Applicable
Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
TOSU
TOSH
TOSL
STKPTR
1220
1220
1220
1220
1320
1320
1320
1320
---0 0000
0000 0000
0000 0000
00-0 0000
---0 0000
0000 0000
0000 0000
00-0 0000
---0 uuuu(3)
uuuu uuuu(3)
uuuu uuuu(3)
uu-u uuuu(3)
PCLATU
1220 1320
---0 0000
---0 0000
---u uuuu
PCLATH
PCL
1220 1320
1220 1320
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PC + 2(2)
TBLPTRU
1220 1320
--00 0000
--00 0000
--uu uuuu
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
1220
1220
1220
1220
1220
1220
1220
1220
1320
1320
1320
1320
1320
1320
1320
1320
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 000x
1111 -1-1
11-0 0-00
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 000u
1111 -1-1
11-0 0-00
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu(1)
uuuu -u-u(1)
uu-u u-uu(1)
INDF0
1220 1320
N/A
N/A
N/A
POSTINC0
1220 1320
N/A
N/A
N/A
POSTDEC0
1220 1320
N/A
N/A
N/A
PREINC0
1220 1320
N/A
N/A
N/A
PLUSW0
1220 1320
N/A
N/A
N/A
FSR0H
1220 1320
---- 0000
---- 0000
---- uuuu
FSR0L
1220 1320
xxxx xxxx
uuuu uuuu
uuuu uuuu
WREG
1220 1320
xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF1
1220 1320
N/A
N/A
N/A
POSTINC1
1220 1320
N/A
N/A
N/A
POSTDEC1
1220 1320
N/A
N/A
N/A
PREINC1
1220 1320
N/A
N/A
N/A
PLUSW1
1220 1320
N/A
N/A
N/A
FSR1H
FSR1L
1220 1320
1220 1320
---- 0000
xxxx xxxx
---- 0000
uuuu uuuu
---- uuuu
uuuu uuuu
Legend:
Note 1:
2:
3:
4:
5:
6:
u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
See Table 4-2 for Reset value for specific condition.
Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the Oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
Bit 5 of PORTA is enabled if MCLR is disabled.
DS39605F-page 36
© 2007 Microchip Technology Inc.
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