PIC18F1220_07 Datasheet, PDF (39/308 Pages) Microchip Technology – 18/20/28-Pin High-Performance, Enhanced Flash Microcontrollers with 10-bit A/D and nanoWatt Technology

PIC18F1220/1320
TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable
Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
BSR
INDF2
1220 1320
1220 1320
---- 0000
N/A
---- 0000
N/A
---- uuuu
N/A
POSTINC2
1220 1320
N/A
N/A
N/A
POSTDEC2
1220 1320
N/A
N/A
N/A
PREINC2
1220 1320
N/A
N/A
N/A
PLUSW2
1220 1320
N/A
N/A
N/A
FSR2H
FSR2L
STATUS
TMR0H
TMR0L
1220
1220
1220
1220
1220
1320
1320
1320
1320
1320
---- 0000
xxxx xxxx
---x xxxx
0000 0000
xxxx xxxx
---- 0000
uuuu uuuu
---u uuuu
0000 0000
uuuu uuuu
---- uuuu
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
T0CON
1220 1320
1111 1111
1111 1111
uuuu uuuu
OSCCON
1220 1320
0000 q000
0000 q000
uuuu qquu
LVDCON
1220 1320
--00 0101
--00 0101
--uu uuuu
WDTCON
RCON⁽⁴⁾
TMR1H
TMR1L
T1CON
TMR2
1220
1220
1220
1220
1220
1220
1320
1320
1320
1320
1320
1320
---- ---0
0--1 11q0
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
---- ---0
0--q qquu
uuuu uuuu
uuuu uuuu
u0uu uuuu
0000 0000
---- ---u
u--u qquu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
PR2
1220 1320
1111 1111
1111 1111
1111 1111
T2CON
1220 1320
-000 0000
-000 0000
-uuu uuuu
ADRESH
1220 1320
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADRESL
1220 1320
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0
ADCON1
ADCON2
CCPR1H
CCPR1L
1220
1220
1220
1220
1220
1320
1320
1320
1320
1320
00-0 0000
-000 0000
0-00 0000
xxxx xxxx
xxxx xxxx
00-0 0000
-000 0000
0-00 0000
uuuu uuuu
uuuu uuuu
uu-u uuuu
-uuu uuuu
u-uu uuuu
uuuu uuuu
uuuu uuuu
CCP1CON
1220 1320
0000 0000
0000 0000
uuuu uuuu
PWM1CON
1220 1320
0000 0000
0000 0000
uuuu uuuu
ECCPAS
1220 1320
0000 0000
0000 0000
uuuu uuuu
Legend:
Note 1:
2:
3:
4:
5:
6:
u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
See Table 4-2 for Reset value for specific condition.
Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the Oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
Bit 5 of PORTA is enabled if MCLR is disabled.
© 2007 Microchip Technology Inc.
DS39605F-page 37