PIC18F1220_07 Datasheet, PDF (53/308 Pages) Microchip Technology – 18/20/28-Pin High-Performance, Enhanced Flash Microcontrollers with 10-bit A/D and nanoWatt Technology

PIC18F1220/1320
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F1220/1320) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details on
POR, BOR page:
TMR1H
Timer1 Register High Byte
xxxx xxxx 37, 108
TMR1L
Timer1 Register Low Byte
xxxx xxxx 37, 108
T1CON
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 37, 103
TMR2
Timer2 Register
0000 0000 37, 109
PR2
Timer2 Period Register
1111 1111 37, 109
T2CON
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 37, 109
ADRESH
A/D Result Register High Byte
xxxx xxxx 37, 164
ADRESL
A/D Result Register Low Byte
xxxx xxxx 37, 164
ADCON0
VCFG1
VCFG0
—
CHS2
CHS1
CHS0 GO/DONE ADON 00-0 0000 37, 155
ADCON1
—
PCFG6
PCFG5
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0 -000 0000 37, 156
ADCON2
ADFM
—
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0 0-00 0000 37, 157
CCPR1H
Capture/Compare/PWM Register 1 High Byte
xxxx xxxx 37. 116
CCPR1L
Capture/Compare/PWM Register 1 Low Byte
xxxx xxxx 37, 116
CCP1CON
P1M1
P1M0
DC1B1
DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 37, 115
PWM1CON PRSEN
PDC6
PDC5
PDC4
PDC3
PDC2
PDC1
PDC0 0000 0000 37, 126
ECCPAS
ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 37, 127
TMR3H
Timer3 Register High Byte
xxxx xxxx 38, 113
TMR3L
Timer3 Register Low Byte
xxxx xxxx 38, 113
T3CON
RD16
—
T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0-00 0000 38, 111
SPBRGH EUSART Baud Rate Generator High Byte
0000 0000
38
SPBRG
EUSART Baud Rate Generator Low Byte
0000 0000 38, 135
RCREG
EUSART Receive Register
0000 0000 38, 143,
142
TXREG
EUSART Transmit Register
0000 0000 38, 140,
142
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D 0000 0010 38, 132
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D 0000 000x 38, 133
BAUDCTL
—
RCIDL
—
SCKP
BRG16
—
WUE
ABDEN -1-1 0-00
38
EEADR
EEPROM Address Register
0000 0000 38, 67
EEDATA
EEPROM Data Register
0000 0000 38, 70
EECON2
EEPROM Control Register 2 (not a physical register)
0000 0000 38, 58, 67
EECON1
EEPGD
CFGS
—
FREE
WRERR
WREN
WR
RD
xx-0 x000 38, 59, 68
IPR2
OSCFIP
—
—
EEIP
—
LVDIP
TMR3IP
—
1--1 -11- 38, 83
PIR2
OSCFIF
—
—
EEIF
—
LVDIF
TMR3IF
—
0--0 -00- 38, 79
PIE2
OSCFIE
—
—
EEIE
—
LVDIE
TMR3IE
—
0--0 -00- 38, 81
IPR1
—
ADIP
RCIP
TXIP
—
CCP1IP TMR2IP TMR1IP -111 -111 38, 82
PIR1
—
ADIF
RCIF
TXIF
—
CCP1IF TMR2IF TMR1IF -000 -000 38, 78
PIE1
—
ADIE
RCIE
TXIE
—
CCP1IE TMR2IE TMR1IE -000 -000 38, 80
OSCTUNE
—
—
TUN5
TUN4
TUN3
TUN2
TUN1
TUN0 --00 0000 38, 15
TRISB
TRISA
Data Direction Control Register for PORTB
TRISA7⁽²⁾ TRISA6⁽¹⁾
—
Data Direction Control Register for PORTA
1111 1111
11-1 1111
38, 98
38, 89
LATB
LATA
Read/Write PORTB Data Latch
LATA<7>⁽²⁾ LATA<6>⁽¹⁾
—
Read/Write PORTA Data Latch
xxxx xxxx
xx-x xxxx
38, 98
38, 89
PORTB
PORTA
Read PORTB pins, Write PORTB Data Latch
RA7⁽²⁾
RA6⁽¹⁾
RA5⁽⁴⁾ Read PORTA pins, Write PORTA Data Latch
xxxx xxxx
xx0x 0000
38, 98
38, 89
Legend:
Note 1:
2:
3:
4:
x = unknown, u = unchanged, – = unimplemented, q = value depends on condition
RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator mode only and read ‘0’
in all other oscillator modes.
RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read ‘0’ in all other modes.
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
The RA5 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’. Otherwise, RA5 reads ‘0’. This bit is read-only.
© 2007 Microchip Technology Inc.
DS39605F-page 51