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| PIC18F1220_07 Datasheet, PDF (9/308 Pages) Microchip Technology – 18/20/28-Pin High-Performance, Enhanced Flash Microcontrollers with 10-bit A/D and nanoWatt Technology | |||
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PIC18F1220/1320
FIGURE 1-1:
PIC18F1220/1320 BLOCK DIAGRAM
Data Bus<8>
21
21
Address Latch
Program Memory
(4 Kbytes)
PIC18F1220
(8 Kbytes)
PIC18F1320
Data Latch
16
21 Table Pointer <2> 8
8
8
inc/dec logic
20 PCLATU PCLATH
PCU PCH PCL
Program Counter
31 Level Stack
Data Latch
8
Data RAM
Address Latch
12(2)
Address<12>
4
BSR
12
FSR0
FSR1
FSR2
4
Bank0, F
12
Table Latch
inc/dec
Decode logic
8
ROM Latch
OSC1(2)
OSC2(2)
T1OSI
T1OSO
MCLR(1)
VDD, VSS
Instruction
Decode &
Control
Instruction
Register
Timing
Generation
INTRC
Oscillator
Low-Voltage
Programming
In-Circuit
Debugger
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Fail-Safe
Clock Monitor
8
PRODH PRODL
3
8 x 8 Multiply
8
BIT OP WREG
8
8
8
8
ALU<8>
8
Precision
Voltage
Reference
PORTA
PORTB
RA0/AN0
RA1/AN1/LVDIN
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
MCLR/VPP/RA5(1)
OSC2/CLKO/RA6(2)
OSC2/CLKI/RA7(2)
RB0/AN4/INT0
RB1/AN5/TX/CK/INT1
RB2/P1B/INT2
RB3/CCP1/P1A
RB4/AN6/RX/DT/KBI0
RB5/PGM/KBI1
RB6/PGC/T1OSO/
T13CKI/P1C/KBI2
RB7/PGD/T1OSI/
P1D/KBI3
Timer0
Timer1
Timer2
Timer3
A/D Converter
Enhanced
CCP
Enhanced
USART
Data EEPROM
Note
1: RA5 is available only when the MCLR Reset is disabled.
2: OSC1, OSC2, CLKI and CLKO are only available in select oscillator modes and when these pins are not being used as digital
I/O. Refer to Section 2.0 âOscillator Configurationsâ for additional information.
© 2007 Microchip Technology Inc.
DS39605F-page 7
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