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PIC18F1220_07 Datasheet, PDF (84/308 Pages) Microchip Technology – 18/20/28-Pin High-Performance, Enhanced Flash Microcontrollers with 10-bit A/D and nanoWatt Technology | |||
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PIC18F1220/1320
9.4 IPR Registers
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are two Peripheral
Interrupt Priority registers (IPR1, IPR2). Using the
priority bits requires that the Interrupt Priority Enable
(IPEN) bit be set.
REGISTER 9-8:
IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
U-0
R/W-1 R/W-1 R/W-1
U-0
R/W-1
â
ADIP
RCIP
TXIP
â
CCP1IP
bit 7
R/W-1
TMR2IP
R/W-1
TMR1IP
bit 0
bit 7
Unimplemented: Read as â0â
bit 6
ADIP: A/D Converter Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5
RCIP: EUSART Receive Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4
TXIP: EUSART Transmit Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3
Unimplemented: Read as â0â
bit 2
CCP1IP: CCP1 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
TMR1IP: TMR1 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
â1â = Bit is set
U = Unimplemented bit, read as â0â
â0â = Bit is cleared x = Bit is unknown
DS39605F-page 82
© 2007 Microchip Technology Inc.
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