PIC18F1220_07 Datasheet, PDF (191/308 Pages) Microchip Technology – 18/20/28-Pin High-Performance, Enhanced Flash Microcontrollers with 10-bit A/D and nanoWatt Technology

19.9 Low-Voltage ICSP Programming
The LVP bit in configuration register, CONFIG4L,
enables Low-Voltage Programming (LVP). When LVP
is enabled, the microcontroller can be programmed
without requiring high voltage being applied to the
MCLR/VPP/RA5 pin, but the RB5/PGM/KBI1 pin is then
dedicated to controlling Program mode entry and is not
available as a general purpose I/O pin.
LVP is enabled in erased devices.
While programming using LVP, VDD is applied to the
MCLR/VPP/RA5 pin as in normal execution mode. To
enter Programming mode, VDD is applied to the PGM
pin.
Note 1: High-voltage programming is always
available, regardless of the state of the
LVP bit or the PGM pin, by applying VIHH
to the MCLR pin.
2: When Low-Voltage Programming is
enabled, the RB5 pin can no longer be
used as a general purpose I/O pin.
3: When LVP is enabled, externally pull the
PGM pin to VSS to allow normal program
execution.
PIC18F1220/1320
If Low-Voltage Programming mode will not be used, the
LVP bit can be cleared and RB5/PGM/KBI1 becomes
available as the digital I/O pin RB5. The LVP bit may be
set or cleared only when using standard high-voltage
programming (VIHH applied to the MCLR/VPP/RA5 pin).
Once LVP has been disabled, only the standard high-
voltage programming is available and must be used to
program the device.
Memory that is not code-protected can be erased,
using either a Block Erase, or erased row by row, then
written at any specified VDD. If code-protected memory
is to be erased, a Block Erase is required. If a Block
Erase is to be performed when using Low-Voltage
Programming, the device must be supplied with VDD of
4.5V to 5.5V.
© 2007 Microchip Technology Inc.
DS39605F-page 189